vhdl and verilog combined in xilinx

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grittinjames

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hai just for fun i written a program containing some modules of verilog and some of vhdl

it given me proper shematic,

but i tried to simuLATE USING modelsim it given me error telling that version support only single hdl

is any way to avoid it
 

The only way to get around this with ModelSim is to upgrade to the PE version.
 

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