LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
ENTITY hazard_unit_forwards IS
PORT (
i_Rs1E, i_Rs2E : IN STD_LOGIC_VECTOR(4 downto 0);
i_RdM, i_RdW : IN STD_LOGIC_VECTOR(4 downto 0);
i_RegWriteM, i_RegWriteW : IN STD_LOGIC;
o_ForwardAE, o_ForwardBE : OUT STD_LOGIC_VECTOR(1 downto 0) -- forward A and B to execute stage
);
END;
ARCHITECTURE behave OF hazard_unit_forwards IS
BEGIN
-- forwarding logic for Rs1E
PROCESS(i_Rs1E, i_RdM, i_RdW, i_RegWriteM, i_RegWriteW) BEGIN
IF(((i_Rs1E = i_RdM) AND i_RegWriteM) AND (i_Rs1E /= "00000")) THEN -- forward from memory stage
o_ForwardAE <= "10";
ELSIF (((i_Rs1E = i_RdW) AND i_RegWriteW) AND (i_Rs1E /= "00000")) THEN -- forward from writeback stage
o_ForwardAE <= "01";
ELSE -- no forwarding (use RF output)
o_ForwardAE <= "00";
END IF;
END PROCESS;
-- forwarding logic for Rs2E
PROCESS(i_Rs2E, i_RdM, i_RdW, i_RegWriteM, i_RegWriteW) BEGIN
IF(((i_Rs2E = i_RdM) AND i_RegWriteM) AND (i_Rs2E /= "00000")) THEN -- forward from memory stage
o_ForwardBE <= "10";
ELSIF (((i_Rs2E = i_RdW) AND i_RegWriteW) AND (i_Rs2E /= "00000")) THEN -- forward from writeback stage
o_ForwardBE <= "01";
ELSE -- no forwarding (use RF output)
o_ForwardBE <= "00";
END IF;
END PROCESS;
END;