mImoto
Full Member level 4
Hello,
I am using the ansoft simplorer SV version that includes a vhdl-ams simulator for learning vhdl-ams.
my problem is that when I write the code below it gives me syntax error and I don't know why. I would appreciate any help.
LIBRARY IEEE;
USE IEEE.ELECTRICAL_SYSTEMS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.MATH_REAL.ALL;
ENTITY schmitt_trigger IS
port (terminal ain: electrical;
signal dout: out std_ulogic);
END ENTITY schmitt_trigger;
ARCHITECTURE behavioral OF schmitt_trigger IS
constant vhi: real:=3.0;
constant vlo: real:=1.7;
quantity vin across ain;
BEGIN
comparator_behaviour: process is
begin
if vin > vhi then
dout <= '1' after 5 ns;
else vin < vlo then
dout <= '0' after 5 ns;
end if;
wait on vin'above(vhi);-- HERE GIVES ME "'" SYNTAX ERROR
end process comparator_behaviour;
END ARCHITECTURE behavioral;
Best regards,
mimoto
I am using the ansoft simplorer SV version that includes a vhdl-ams simulator for learning vhdl-ams.
my problem is that when I write the code below it gives me syntax error and I don't know why. I would appreciate any help.
LIBRARY IEEE;
USE IEEE.ELECTRICAL_SYSTEMS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.MATH_REAL.ALL;
ENTITY schmitt_trigger IS
port (terminal ain: electrical;
signal dout: out std_ulogic);
END ENTITY schmitt_trigger;
ARCHITECTURE behavioral OF schmitt_trigger IS
constant vhi: real:=3.0;
constant vlo: real:=1.7;
quantity vin across ain;
BEGIN
comparator_behaviour: process is
begin
if vin > vhi then
dout <= '1' after 5 ns;
else vin < vlo then
dout <= '0' after 5 ns;
end if;
wait on vin'above(vhi);-- HERE GIVES ME "'" SYNTAX ERROR
end process comparator_behaviour;
END ARCHITECTURE behavioral;
Best regards,
mimoto