Nov 6, 2018 #1 W wtr Full Member level 5 Joined May 1, 2014 Messages 299 Helped 29 Reputation 58 Reaction score 25 Trophy points 1,308 Activity points 4,108 Hello all, We've got a board where the test_leds have been routed terribly. TEST_LEDS(9 downto 0) are wired in a scattered format Looks something like this (3)--------(8) (8)--------(5) (4)--------(2) (9)--------(1) (0)--------(7) I want to be able to generate an alias name that can be assigned using slicing. The following is the alias syntax rule Code: alias_declaration ::= alias alias_designator [ : subtype_indication ] is name [ signature ] ; alias_designator ::= identifier | character_literal | operator_symbol Code VHDL - [expand]1 alias led : std_logic_vector(TEST_LEDS'range) is xxx Where I want xxx to be test_led(0) & test_led(9) etc I know the following works but it doesn't give me the std_logic_vector I want for slicing. Code VHDL - [expand]1 2 alias led9 : std_logic is test_led(0); alias led8 : std_logic is test_led(9); Regards
Hello all, We've got a board where the test_leds have been routed terribly. TEST_LEDS(9 downto 0) are wired in a scattered format Looks something like this (3)--------(8) (8)--------(5) (4)--------(2) (9)--------(1) (0)--------(7) I want to be able to generate an alias name that can be assigned using slicing. The following is the alias syntax rule Code: alias_declaration ::= alias alias_designator [ : subtype_indication ] is name [ signature ] ; alias_designator ::= identifier | character_literal | operator_symbol Code VHDL - [expand]1 alias led : std_logic_vector(TEST_LEDS'range) is xxx Where I want xxx to be test_led(0) & test_led(9) etc I know the following works but it doesn't give me the std_logic_vector I want for slicing. Code VHDL - [expand]1 2 alias led9 : std_logic is test_led(0); alias led8 : std_logic is test_led(9); Regards
Nov 6, 2018 #2 T TrickyDicky Advanced Member level 7 Joined Jun 7, 2010 Messages 7,110 Helped 2,081 Reputation 4,181 Reaction score 2,048 Trophy points 1,393 Activity points 39,769 For this, you'd probably be better off just creating a slv signal and assigning the leds in a more suitable order. You can only alias to existing objects.
For this, you'd probably be better off just creating a slv signal and assigning the leds in a more suitable order. You can only alias to existing objects.
Nov 7, 2018 #3 V vGoodtimes Advanced Member level 4 Joined Feb 16, 2015 Messages 1,089 Helped 307 Reputation 614 Reaction score 303 Trophy points 83 Activity points 8,730 I would either have a permutation function, do the permutation elsewhere at the top level, or do the permutation in the xdc file.
I would either have a permutation function, do the permutation elsewhere at the top level, or do the permutation in the xdc file.
Nov 7, 2018 #4 W wtr Full Member level 5 Joined May 1, 2014 Messages 299 Helped 29 Reputation 58 Reaction score 25 Trophy points 1,308 Activity points 4,108 So, The following is allowed because TEST_LEDS object exists, even if we've switched range ascending/deceasing and sliced it. Code VHDL - [expand]1 2 alias leds : std_logic_vector(3 downto 0) is TEST_LEDS(3 downto 0); alias leds2 : std_logic_vector(3 downto 0) is TEST_LEDS(4 to 7); However one cannot create a """new""" object by concatenating a selection of objects? alias leds : std_logic_vector(7 downto 0) is TEST_LEDS(4 to 7) & TEST_LEDS(3 downto 0); An object is (a constant, variable signal or a file) <- basically stuff before the begin keyboard in architecture body. This is a shame. Was aware of the slv method, but was trying to do something clever/pushing the language.
So, The following is allowed because TEST_LEDS object exists, even if we've switched range ascending/deceasing and sliced it. Code VHDL - [expand]1 2 alias leds : std_logic_vector(3 downto 0) is TEST_LEDS(3 downto 0); alias leds2 : std_logic_vector(3 downto 0) is TEST_LEDS(4 to 7); However one cannot create a """new""" object by concatenating a selection of objects? alias leds : std_logic_vector(7 downto 0) is TEST_LEDS(4 to 7) & TEST_LEDS(3 downto 0); An object is (a constant, variable signal or a file) <- basically stuff before the begin keyboard in architecture body. This is a shame. Was aware of the slv method, but was trying to do something clever/pushing the language.
Nov 7, 2018 #5 T TrickyDicky Advanced Member level 7 Joined Jun 7, 2010 Messages 7,110 Helped 2,081 Reputation 4,181 Reaction score 2,048 Trophy points 1,393 Activity points 39,769 why not just create another signal? It really isnt any different to what you're doing.
Nov 8, 2018 #6 W wtr Full Member level 5 Joined May 1, 2014 Messages 299 Helped 29 Reputation 58 Reaction score 25 Trophy points 1,308 Activity points 4,108 TrickyDicky, It's not about getting to the destination. IT's about the journey.
Nov 9, 2018 #7 V vGoodtimes Advanced Member level 4 Joined Feb 16, 2015 Messages 1,089 Helped 307 Reputation 614 Reaction score 303 Trophy points 83 Activity points 8,730 Sometimes, during the journey, an npc suggests adding a layer of indirection. Upon completing this quest you gain +1 wisdom.
Sometimes, during the journey, an npc suggests adding a layer of indirection. Upon completing this quest you gain +1 wisdom.