Oct 11, 2012 #1 S shaiko Advanced Member level 5 Joined Aug 20, 2011 Messages 2,644 Helped 303 Reputation 608 Reaction score 297 Trophy points 1,363 Activity points 18,302 Are VHDL aliases always synthesizable ?
Oct 11, 2012 #2 S std_match Advanced Member level 4 Joined Jul 9, 2010 Messages 1,306 Helped 463 Reputation 926 Reaction score 448 Trophy points 1,363 Location Sweden Activity points 10,197 One experience I have had is that I could leave out the optional subtype indication in Modelsim but the synthesis tool required it.
One experience I have had is that I could leave out the optional subtype indication in Modelsim but the synthesis tool required it.
Oct 11, 2012 #3 T TrickyDicky Advanced Member level 7 Joined Jun 7, 2010 Messages 7,110 Helped 2,081 Reputation 4,181 Reaction score 2,048 Trophy points 1,393 Activity points 39,769 My Doulos golden reference guid recommends not using them, but it is a few years old now. I would probably stear away from them, because I cant think of any situation where an alias is a neccessity.
My Doulos golden reference guid recommends not using them, but it is a few years old now. I would probably stear away from them, because I cant think of any situation where an alias is a neccessity.