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vhdl: addressing rom

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katkacyt

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Hi,
i'm trying to make a std_ulogic_vector - addressable ROM, but i've got problem with code:


Code VHDL - [expand]
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entity rom_opcode is
    port ( 
      adr_i         : in opcode_t;             --! address is opcode of instruction
      inst_o                : out instName_t     --! output is a type of instruction 
    );
end rom_opcode;
architecture be_rom_opcode of rom_opcode is
  type rom_t is array (0 to (2**OP_CODE_W)  - 1) of instName_t; 
  constant opcodeRom : rom_t := (
    001000010000 to 001000011111 => ANDS_IMM,
    to_integer(unsigned(std_ulogic_vector'("001000010000"))) to to_integer(unsigned(std_ulogic_vector'("001000011111"))) => ANDS_IMM,
    others => UNDEF);
begin
    inst_o <= opcodeRom(to_integer(unsigned(adr_i)));   
end architecture be_rom_opcode; 
 
 
( OP_CODE_W defined in a package => constant OP_CODE_W : natural := 12; 
 opcode_t defined in a package => subtype opcode_t is std_ulogic_vector(OP_CODE_W - 1 downto 0);
 instName_t defined in a package => type instName_t is (ANDS_IMM, ... , UNDEF);)


but there are more problems:
first version gives "static range violates bounds"
second version gives "not static choice exclude others choice; non-locally static choice for an aggregate is allowed only if only choice"

and, concerning rom bounds i've got warning "universal integer bound must be numeric literal or attribute"

any help will be welcomed...
 
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TrickyDicky

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Yes.
range indeces are in decimal by default, so 001000010000 is 10 billion, 10 thousand. Not the binary form (this is larger than the range of integer). You need to format the number with:

2#00100001000# to make it a binary representation of an integer (or 16#208# if you want hex)

and I think the error comes from using the to_integer function - the rules say the values need to be static (function call isnt static).
 

katkacyt

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Yes.
range indeces are in decimal by default, so 001000010000 is 10 billion, 10 thousand. Not the binary form (this is larger than the range of integer). You need to format the number with:

2#00100001000# to make it a binary representation of an integer (or 16#208# if you want hex)

and I think the error comes from using the to_integer function - the rules say the values need to be static (function call isnt static).

that works, thanks a lot!
the only thing now is that warning "warning: universal integer bound must be numeric literal or attribute" for line

Code VHDL - [expand]
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type rom_t is array (0 to (2**OP_CODE_W)  - 1) of instName_t; --! rom containing instruction names


would you have a hint?
 

TrickyDicky

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Are you sure it's pointing to that line?

Could you post the whole code so I can try it here?
 

katkacyt

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Are you sure it's pointing to that line?

Could you post the whole code so I can try it here?


i'm sure it's that line
it's quite a big project, so there are dozen of files, but maybe this'll be enough?

rom_opcode.vhd:


Code VHDL - [expand]
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--
--
 
-----------------------------------------------------------------
-----------------------------------------------------------------
--                                                             
--! @file rom_opcode.vhd                                                            
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library proc_lib;
-- use proc_lib.core_pack.all;
use proc_lib.isa.all;
 
-- library config_lib;
-- use config_lib.config.all;
 
 
 
 
entity rom_opcode is
    port ( 
      adr_i         : in opcode_t;             --! address is opcode of instruction
      inst_o        : out instName_t           --! output is a type of instruction 
    );
end rom_opcode;
 
architecture be_rom_opcode of rom_opcode is
  type rom_t is array (0 to (2**OP_CODE_W)  - 1) of instName_t; 
  constant opcodeRom : rom_t := (
    -- bits 27-20 = X"00"
    2#0000_0000_0000# => AND_LLI,                   -- X"000"
    2#0000_0000_0001# => AND_LLR,                   -- X"001"
    2#0000_0000_0010# => AND_LRI,                   -- X"002"    
    2#0000_0000_0011# => AND_LRR,                   -- X"003"    
    2#0000_0000_0100# => AND_ARI,                   -- X"004"
    2#0000_0000_0101# => AND_ARR,                   -- X"005"
    2#0000_0000_0110# => AND_RRI,                   -- X"006"    
    2#0000_0000_0111# => AND_RRR,                   -- X"007"
    2#0000_0000_1000# => AND_LLI,                   -- X"008"
    2#0000_0000_1001# => MUL,                       -- X"009"
    2#0000_0000_1010# => AND_LRI,                   -- X"00A"    
    2#0000_0000_1011# => STRH_PTRM,                 -- X"00B"    
    2#0000_0000_1100# => AND_ARI,                   -- X"00C"
    2#0000_0000_1101# => UNDEF,                     -- X"00D"       opcode defined only in M-extension (LDRD ptrm)
    2#0000_0000_1110# => AND_RRI,                   -- X"00E"    
    2#0000_0000_1111# => UNDEF,                     -- X"00F"       opcode defined only in M-extension (STRD ptrm)
    -- ......
    -- bits 27-20 = X"20"
    2#0010_0000_0000# to 2#0010_0000_1111# => AND_IMM,                      -- X"200" to X"20F"
    -- ....
    others => UNDEF);
 
begin
    inst_o <= opcodeRom(to_integer(unsigned(adr_i)));   
end architecture be_rom_opcode;





isa.vhd:



Code VHDL - [expand]
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--
 
library ieee;
use ieee.std_logic_1164.all;
--
--! The package implements usefull defines for the armv7 
--! Instruction Set Assembly (ISA).
--
--! ISA Package
package isa is 
  type instName_t is (AND_LLI, AND_LLR, AND_LRI, AND_LRR, AND_ARI, AND_ARR, AND_RRI, AND_RRR, 
                        ANDS_LLI, ANDS_LLR, ANDS_LRI, ANDS_LRR, ANDS_ARI, ANDS_ARR, ANDS_RRI, ANDS_RRR,
                        AND_IMM, ANDS_IMM,
                        EOR_LLI, EOR_LLR, EOR_LRI, EOR_LRR, EOR_ARI, EOR_ARR, EOR_RRI, EOR_RRR,
                        EORS_LLI, EORS_LLR, EORS_LRI, EORS_LRR, EORS_ARI, EORS_ARR, EORS_RRI, EORS_RRR,
                        EOR_IMM, EORS_IMM,
                        SUB_LLI, SUB_LLR, SUB_LRI, SUB_LRR, SUB_ARI, SUB_ARR, SUB_RRI, SUB_RRR, 
                        SUBS_LLI, SUBS_LLR, SUBS_LRI, SUBS_LRR, SUBS_ARI, SUBS_ARR, SUBS_RRI, SUBS_RRR,
                        SUB_IMM, SUBS_IMM,
                        RSB_LLI, RSB_LLR, RSB_LRI, RSB_LRR, RSB_ARI, RSB_ARR, RSB_RRI, RSB_RRR, 
                        RSBS_LLI, RSBS_LLR, RSBS_LRI, RSBS_LRR, RSBS_ARI, RSBS_ARR, RSBS_RRI, RSBS_RRR, 
                        RSB_IMM, RSBS_IMM,
                        MUL, MULS,
                        MLA, MLAS,
                        STRH_PTRM, STRH_PTIM,
                        LDRH_PTRM, LDRSB_PTRM, LDRSH_PTRM, LDRH_PTIM, LDRSB_PTIM, LDRSH_PTIM,
                        EOR, SUB, RSB, ADD, ADC, SBC, RSC, TST, TEQ, CMP, CMN, ORR, MOV, BIC, MVN, 
                        UNDEF);
  
 
  constant OP_COND_W : natural := 4;            --! condition field width
  subtype op_cond_t is std_ulogic_vector(OP_COND_W - 1 downto 0); --! instruction condition field
 
  constant OP_CODE_W : natural := 12;   --! bits 27:20 and 7:4  
  subtype opcode_t is std_ulogic_vector(OP_CODE_W - 1 downto 0); --! cpu opcode type
  
  type cond_t is (EQ, NE, CS, CC, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL);
 
 
 
end package isa;




and my makefile:


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all:
        # ...
    ghdl -a --workdir=bin --work=proc_lib -Pbin src/proc_lib/isa.vhd 
    ghdl -a --workdir=bin --work=proc_lib -Pbin src/proc_lib/rom_opcode.vhd



i'll profit to ask another question:
is it better - in terms of hardware occupation and complexity - to make a ROM who contains opcode and control signals or a ROM who contains only instruction name and forward it to a case / if construction who assignes control signals?
 

TrickyDicky

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It does seem like an odd warning - but only a warning.

As for your rom - It depends how the synthesisor decides to encode the opcodes - try both and check the ram usage.
 

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