Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] VHDL addition "1111"+"1111"=FAIL

Status
Not open for further replies.

hardware_guy

Newbie level 6
Joined
Aug 22, 2013
Messages
12
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
134
Hi.
I will explain my problem simply.
I'm trying to get summary of 4-bit vectors in one, 8-bit vector.


Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
signal cnt1,cnt2,cnt3,cnt4,cnt5 : STD_LOGIC_VECTOR (3 downto 0);
signal count                  : STD_LOGIC_VECTOR (7 downto 0);
 
cnt1 <= "0000";
cnt2 <= "0000";
cnt3 <= "0000";
cnt4 <= "0001";
cnt5 <= "1111";
 
count <= cnt1 + cnt2 + cnt3 + cnt4 + cnt5;



I'm expecting to get "00010000" on "count", but I get "00000000"

When I tried this:


Code VHDL - [expand]
1
count <= "0000"&cnt1 + "0000"&cnt2 + "0000"&cnt3 + "0000"&cnt4 + "0000"&cnt5;



I got "00011111"

Yes, I have read recomendations, to use differnt library or use "integer", but I still fail to understand.
I add this:


Code VHDL - [expand]
1
2
3
4
5
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;



Is it not enough, or is it too much? How to get "00010000" in this example? How to use "integer" in this example?
In my project, each of the counters cnt1-cnt5 will have own reset signal, but I want to join them in to one vector, to make future processing. :-?
 

vGoodtimes

Advanced Member level 4
Joined
Feb 16, 2015
Messages
1,089
Helped
307
Reputation
614
Reaction score
302
Trophy points
83
Activity points
8,730
https://www.csee.umbc.edu/portal/help/VHDL/operator.html

"+" has higher precedence than "&". thus you get:
Code:
count <= "0000" & (cnt1+"0000") & (cnt2+"0000") & (cnt3+"0000") & (cnt4+"0000") & cnt5;
-- "0000" & "0000" & "0000" & "0000" & "0001" & "1111"
-- one of the std_logic_* packages must allow the assignment to work despite the bit-width difference.

-- you want
count <= ("0000"&cnt1) + ("0000"&cnt2) + ("0000"&cnt3) + ("0000"&cnt4) + ("0000"&cnt5);
 

TrickyDicky

Advanced Member level 5
Joined
Jun 7, 2010
Messages
7,065
Helped
2,077
Reputation
4,171
Reaction score
2,030
Trophy points
1,393
Activity points
39,119
why not using unsigned in stead of std_logic_vector for cnt and count?

This would make sense from a standard VHDL point of veiw (assuming the OP got rid of std_logic_arith to ensure there were no clashes). But you would still have exactly the same problem.
 

lucbra

Advanced Member level 2
Joined
Oct 30, 2003
Messages
514
Helped
73
Reputation
146
Reaction score
63
Trophy points
1,308
Location
Belgium
Activity points
3,251
Re: VHDL addition &quot;1111&quot;+&quot;1111&quot;=FAIL

yes true for the second piece of code - I was referring to the original part in post #1.
'+' has higher precedence than '&'
 

FvM

Super Moderator
Staff member
Joined
Jan 22, 2008
Messages
48,427
Helped
14,252
Reputation
28,765
Reaction score
12,942
Trophy points
1,393
Location
Bochum, Germany
Activity points
280,223
Presuming the poster want to learn reasonable VHDL coding style instead of using outdated libraries, I would suggest (with unsigned type for all signals)
Code:
count <= resize(cnt1,8) + cnt2 + cnt3 + cnt4 + cnt5;

The other summands are automatically resized to 8-bit unsigned before being added. The advantage of resize() is that it also peforms sign extension for signed signals.
 

hardware_guy

Newbie level 6
Joined
Aug 22, 2013
Messages
12
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
134
Thank you all. Your replies have helped me to solve my problem.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top