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VHDL 3D array input port

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shaiko

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Hello,

Is it possible to define a 3D unconstrained array as an input port to a VHDL entity?
for example - inside a package
Code:
type unconstrained_2D_array : is array ( natural range <> ) of std_logic_vector ;
type unconstrained_3D_array : is array ( natural range <> ) of unconstrained_2D_array ;
If I use the custom type "unconstrained_3D_array" as an input port to an entity - will it synthesize?
 

barry

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I'm not sure you can use ANY unconstrained port on an entity. But I would say, 'why don't you just try it and see what happens?'
 

TrickyDicky

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It's allowed by VHDL 2008 , but I wouldnt count on support from synthesis vendors...
 
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    shaiko

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