type input_port_array is array ( 0 to 255 ) of std_logic_vector ( 31 downto 0 ) ;
type input_port_array is array ( natural range <> ) of std_logic_vector <> ;
type input_port_array is array ( natural range <> ) of std_logic_vector ;
type input_port_array is array ( [COLOR="#FF0000"]unsigned[/COLOR] range <> ) of std_logic_vector ;
entity some_entity is
port (
a : std_logic_vector --look, no length declared!
b : unsigned
c : signed
)
signal x : std_logic_vector(7 downto 0);
signal y : unsigned(65 downto 43);
signal z : signed(9999999 to 10000000);
inst1 : entity work.some_entity
port map (
a => x,
b => y,
c => z
);
type my_array is array(natural length <>) of std_logic_vector; --illegal in '93
type my_record is
a : std_logic_vector; --again, illegal in '93
end record my_record;
suppose you use an unconstrained array (defined in a package) as an input port to an entity.And slv/unsigned/sign or any array are not allowed to be unconstrained when they are instantiated
Hierarchy does not matter. Whenever you compile anything, before you can use something it must have been defined previously. If the 'array input port' is a custom thing defined in your own package then you must first 'use work.my-package.all' first. The ordering of files is generally called 'compilation order' whereas 'hierarchy' refers to levels in a design.suppose you use an unconstrained array (defined in a package) as an input port to an entity.
If this "array input port" resides in a lower hierarchy there's no problem - it gets constrained according to the element assigned to it.
But what if this "array input port" resides in the top hierarchy? Compilation error?
Counterquestion. What do you think how it should be used? In which situation would you want an unconstrained array port in the top entity?My question: what if this unconstrained array is an entity input port that resides in the topmost hierarchy?
Surely there's non. I'm just asking to know "what if".I'm not aware of a VHDL means to set the actual array bounds in this situation. I assume, there is no reasonable use for an unconstraint external port.
My question: what if this unconstrained array is an entity input port that resides in the topmost hierarchy?
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