Jan 19, 2017 #1 S shaiko Advanced Member level 5 Joined Aug 20, 2011 Messages 2,644 Helped 303 Reputation 608 Reaction score 297 Trophy points 1,363 Activity points 18,302 Hello, Does VHDL 2008 have special syntax to invert a bus of data like this? Code: invert_bus: for index in data_in ' range generate data_out ( index ) <= not data_in ( index ) ; end generate ;
Hello, Does VHDL 2008 have special syntax to invert a bus of data like this? Code: invert_bus: for index in data_in ' range generate data_out ( index ) <= not data_in ( index ) ; end generate ;
Jan 19, 2017 #2 T TrickyDicky Advanced Member level 7 Joined Jun 7, 2010 Messages 7,110 Helped 2,081 Reputation 4,181 Reaction score 2,048 Trophy points 1,393 Activity points 39,769 yes - its existed since the start of std_logic_1164 for std_logic_vector and 1987 for bit_vector: data_out <= not data_in;
yes - its existed since the start of std_logic_1164 for std_logic_vector and 1987 for bit_vector: data_out <= not data_in;