Hi.
JoannesPaulus said:
Maybe a simplification will show you the feedback path.
One remark. Non-inverting input of the amplifier must be connected to a voltage source Vgs instead of ground.
palmeiras said:
The paper - that proposes this circuit - reports that the dominant pole of this circuit is given by:
wGBW1 = [(gm1*gm2*R1)/Cc1]*(S4/S3)
I have some doubts about it. If possible, could you give some insight about it? I would be very very very glad.
(1) Do you know how they calculated this?
I can draw the small signal model for all transistors. After calculating the transfer function, I will discover the poles and zero. However, I dont know which are the input and output of this circuit. So, how can I calculate the transfer function?
wGBW1 (gain-bandwidth product) is defined as product of DC gain and bandwidth (BW, -3 dB frequency): wGBW = [DC gain]*[BW].
You asked where was input and where was output, or in other words how is defined gain in this circuit. This circuit is DC current source with feedback network. The only gain which makes sense in this circuit is
loop gain (LG). It can be found as product of gain of the voltage amplifier (M1, IB), transconductance gain of transconductance amplifier (M2, M3), gain of the current mirror (M3, M4) and equivalent impedance to ground from node where gate of M4 and R1 are connected : LG = [gain of M1, IB]*[transconductance of M2, M3]*[gain of M3, M4]*[output resistance of (M4, R1)]. Obviously DC loop gain is equal to products of DC gains. DC gain of (M1, IB) is gm1*ro1. DC transconductance of (M2, M3) is gm2 (more precisely gm2*ro2/[ro2 + (1/gm3||ro3)], but ro >> 1/gm in most cases). DC gain of M3, M4 is equal to ratio of aspect ratios of M4 and M3 - S4/S3. Output resistance of (M4, R1) is R1||ro4. These results yields DC loop gain = ro1*gm1*gm2*(R1||ro4)*(S4/S3).
Next step is determination of bandwidth of this circuit. I don’t suggest you to use direct small-signal analysis for this purpose. It's extremely hard work (when number of transistors is greater than one). There are much simpler intuitive methods which are more appropriate for hand analysis. One of such methods is described in Razavi's "Design of Analog CMOS Integrated Circuits" (section 6.1.2 "Association of Poles with Nodes"). Application of this method gives three poles: |p1| = 1/(ro1*Ceq1), |p2| = 1/(ro4||R1*Ceq2), |p3| = 1/[(1/gm2||1/gm3)*Ceq3], where Ceq are equivalent capacitances to ground from corresponding nodes. ro >> 1/gm and Ceq2 ~ Ceq3, so |p2| << |p3| and third pole will be ignored. If we assume that ro4 >> R1 and Cc1 >> all other capacitances at this node, than p1 will appear to be dominant one (also note that equivalent resistance to ground from node where gate of M4 and R1 are connected will be equal to R1 instead of (R1||ro4)). If the circuit has only one dominant pole and no dominant zeros, -3 dB frequency (bandwidth) will be equal to the frequency of that dominant pole. Thus bandwidth of this circuit is equal to BW = 1/(ro1*Cc1) rads/s.
wGBW1 = [DC gain]*[BW] = [ro1*gm1*gm2*R1*(S4/S3)]*[1/(ro1*Cc1)] = gm1*gm2*R1*(S4/S3)/Cc1.
palmeiras said:
(2) The author suggests setting Cc1 in order to maintain wGBW1 well below the value of other remaining poles. Following this recommendation, my circuit will have improved gain-bandwidth product.
I did not understand why the author is talking about gain-bandwidth product when this output voltage provided by this circuit is DC.
Decreasing value of dominant pole (and thus decreasing value of gain-bandwidth product) increases stability of the circuit.
palmeiras said:
What would I improve in the circuit if I follow this recommendation?
Increase Cc1 until phase margin of the loop reaches some acceptable value (typically 45 or 60 degrees).
palmeiras said:
(3) How could I measure the stability of this circuit? And check if the circuit is stable, and its phase margin?
Loop gain simulation
If your simulator is spectre, you can use stability analysis.