VGA interface using DB15 connector in VHDL

[rajavel.rv]

Hi Guys, we are having a doubt to interface with VGA using DB15 connector it having the input and output pins of hsync, vsync, red, green, blue, all will be single bit,.

we are given hsync and vsync properlly, but the problem is how can we are given data to this device, because we are converting the jpeg image to hex format, and loaded that data to memory and given it to be serially, such as, FF 00 48 00 FF 64 74 00 32, etc.,

we are taken the first three byte of FF 00 48 and given serially using shift register to send the data out, here we are taken FF is RED, 00 is Green, 48 is blue, this format is correct or not,.

Thanks & Regards
Rajavel Ashokraj

 

[Dan Mills]

The RG&B signals should be analogue for standard 15 pin VGA, you need a video DAC between your data source and the VGA connector.

DVI/HDMI are digital links, but VGA is analogue in normal use.

With a single bit you have only two levels, so while you can produce an image it will be only 8 colour, and I would suggest that if doing this you preprocess your 24 bit image down to one bit per pixel (Dithering will make it look slightly less awful).

Regards, Dan.

 

[D.A.(Tony)Stewart]

Normally a pixel clock is derived from HS or it is fixed and generates the HS clock.

the Pixel clock must include all the display pixels and the blanking equivalent number of pixels for the blank interval.

The blanking interval includes step before sync, after sync, and sync pulse and is limited to a range to allow monitor to PLL sync to VS, HS and Pixel clock as a number Nx and phase value. Normally at least 5% variation is expected in monitors for PLL pixel clock, some can handle more for each HS and VS range.

Monitors and TV's require some image to detect the pixel clock rate and will auto resync if it guesses wrong on a black image on start up unless it has non-volatile memory.

Overall Pixel clock is defines max resolution possible of the image for a given refresh rate (VS)

e.g. VGA is 640x480= 307.2 kpix
QVGA is 1/4 of VGA
std 1080p monitors today are 2Mpix (1920x1080) and some are 8 MPix 2x resolution and 4x as many pixels

A 3 DAC output drives each analog output at the pixel rate for R,G,B up to 1V (typ) into 75 Ohms.

 

[rajavel.rv]

Yes, but our board not having the DAC in between FPGA to VGA connector, they are directly connected 5 signals(hsync, vsync, r, g, b) to FPGA, how can am given the data as BYTE to BIT,.

 

[D.A.(Tony)Stewart]

DB15 uses analog so you need a Video DAC with 3 outputs