The power failure signal might be a simple voltage divider on the main power capacitor.
The idea of this simple detector is to trigger the MCU when the voltage on this capacitor is at the minimum permissible value.
Perhaps one may like to add an npn transistor to increase the signal slope (at the MCU pin) in the detection range.
Another method is detecting the missing of the first half cycle from mains.
In special applications, one may use both methods and the MCU is triggered for power failure by either of the two.
I think in your case the first one is enough.
Now let us see what comes next, I mean in the interrupt routine.
The first thing to do is to change the MCU ports state so that the circuit current becomes minimal. This helps slowing the power capacitor discharge hence getting more time to continue the memory writing.
I am afraid that the design details depend on many factors related to your actual board which are unknown.
Personal:
About 17 years ago, I faced this problem when I designed my first sat dish positioner. I had Z80 and EPROM only (like 27C512) for its instructions. Obviously every time the set was turned off, its final status had to be saved (about 3 bytes if I remember well). So I built in each set an EPROM programmer (parallel type at that time) which should work just after the mains is cut (usually by the user). I sold about 400 sets before updating it by using EEPROM then SEEP (as 24C16).
To FvM... yes, after about 20,000 cuts the EPROM would become full hence useless :grin: this could happen after 10 years with an average of 5 cuts/day. That is why no user complained :wink:
Kerim