very strange typecast (VHDL)

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hello,

I just noticed this port map in the project I am working on:

Code VHDL - [expand]
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custom_fifo
        PORT map(
          clk                            => clk,
            . . .
          std_logic_vector(q)            => q
        );


I have never seen such a thing. What's its purpose, how does it work, how is this called? If this was to convert from one signal type to another I'd rather do it this way:

Code VHDL - [expand]
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custom_fifo
        PORT map(
          clk                      => clk,
            . . .
          q      => std_logic_vector(q)
        );


Is it perhaps equivalent?
 

Read about named versus positional association in component instantiation.

Both example codes have syntax error, missing delimiting ",".
 

It was done like this because I assume the local version of q was a slv, while the q in the port map is signed/unsigned. You have to do the conversion on the LHS otherwise it is an illegal assignment.
 
I realised now I wasn't very clear in my question. The question was related to type conversion, not port assotiations, sorry

The missing "," is not a syntax error, " . . . " is (it was on purpose).

yes, the conversion is neccessary due to type difference in port / signal.

LHS conversions are very rarely used, seems like I forgot about this feature.

Thank you guys ;-)
 

guess I'd need the help of you guys once more on this topic:
Code VHDL - [expand]
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signal   DQ                        :   std_ulogic_vector( 7 downto 0);
 
-- memory simulation model
inst_name : entity_name
   Port map ( 
      E_b                     => CSN(0),
      W_b                     => WEN,
      G_b                     => OEN,
      A                       => std_logic_vector(Addr(16 downto 0)),
      std_ulogic_vector(DQ)   => std_logic_vector(DQ (7 downto 0))
   );

The component ports are of type std_logic, the signals connected to the instance are of type ulogic.

That works fine for all ports of type IN or OUT, but port DQ is of type INOUT.
So I converted the signal on both sides, once for input once for output.
This compiles fine as long as the signal is 'floating' (not connected anywhere).
As soon as I connect it with a port of another instance I get the error:

I get the following error: "DQ(7)" has multiple drivers but is not a resolved signal.

Can you help?

many thanks
 

Because it is an inout, it implies DQ will be driving from multiple places. So here, DQ will need to be connected to a std_logic_vector, not a ulogic, as ulogic is not a resolved type (std_logic is)
 
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