yannoo@Ubuntoo:~/dev/FPGA$ make test
iverilog -o test counter.vl test.vl
vvp test
At time 0, value = xx (x)
At time 17, value = 00 (0)
At time 35, value = 01 (1)
At time 45, value = 02 (2)
At time 55, value = 03 (3)
At time 57, value = 00 (0)
At time 75, value = 01 (1)
At time 85, value = 02 (2)
At time 95, value = 03 (3)
At time 105, value = 04 (4)
At time 115, value = 05 (5)
At time 125, value = 06 (6)
At time 135, value = 07 (7)
At time 145, value = 08 (8)
At time 155, value = 09 (9)
At time 165, value = 0a (10)