Veriog initiating module in always loop.

[Pedz]

Hi I know it is not possible to initiate a module in an always or if loop, however what is the correct way to go about this problem?:

I have a module that has 4 inputs and 3 outputs. It has to complete 16 times, using the three outputs from the previous initiation for 3 of the inputs to the next. The fourth input being a counter.
I would like it to initiate the module at each clock posedge (so using always @ (posedge)).

I thought it would go:

always @(posdge clk) begin

     module(input1,2,3,4,output1,2,3);
     assign input1 =output1;
     assign input2 =output2;
     assign input3 =output3;
     assign input4 = input4+1:

end

Hoping it would at each posedge of the clock, cycle through the above?


I tried initiating the module in a task/function as well, not really understanding them either at the moment...

Sorry for being so vague, but I would prefer a general answer than a direct answer, so in the future I know what to do/understand it a bit more.
Thanks for any help!

 

[blooz]

always @(posdge clk) begin

module(input1,2,3,4,output1,2,3);
assign input1 =output1;
assign input2 =output2;
assign input3 =output3;
assign input4 = input4+1:

end

module(input1,2,3,4,output1,2,3);
always @(posdge clk) begin
      output1=input1;
      output2=input2;
       output3=input3;
      output4 = input4+1:
end

---------- Post added at 07:20 ---------- Previous post was at 07:05 ----------

Hi I know it is not possible to initiate a module in an always or if loop, however what is the correct way to go about this problem?:

I have a module that has 4 inputs and 3 outputs. It has to complete 16 times, using the three outputs from the previous initiation for 3 of the inputs to the next. The fourth input being a counter.
I would like it to initiate the module at each clock posedge (so using always @ (posedge)).

I thought it would go:

always @(posdge clk) begin

     module(input1,2,3,4,output1,2,3);
     assign input1 =output1;
     assign input2 =output2;
     assign input3 =output3;
     assign input4 = input4+1:

end

Hoping it would at each posedge of the clock, cycle through the above?


I tried initiating the module in a task/function as well, not really understanding them either at the moment...

Sorry for being so vague, but I would prefer a general answer than a direct answer, so in the future I know what to do/understand it a bit more.
Thanks for any help!

you can use some register to store the iteration state ,if you want the always block to be executed till the count=16 ,Use if Statement .

 

[Pedz]

module(input1,2,3,4,output1,2,3);
always @(posdge clk) begin
      output1=input1;
      output2=input2;
       output3=input3;
      output4 = input4+1:
end

---------- Post added at 07:20 ---------- Previous post was at 07:05 ----------



you can use some register to store the iteration state ,if you want the always block to be executed till the count=16 ,Use if Statement .

reg output1;
reg output2;
reg output3;

module(a.(input1),.b(2),.c(3),.d(4),.e(output1),.f(2),.g(3));
always @(posdge clk) begin
   if (ack ==0) begin 
      if (req ==1)
          if(input4==16) begin
             assign ack =1;
          end else begin
             output1=input1;
             output2=input2;
             output3=input3;
             output4 = input4+1:
          end
      end
   end else begin
   assign req = 0;
   end
end

(where ack=1 triggers the end of the sequence) I now seem to get the errors:
error: reg output1; cannot be driven by primitives or continuous assignment.
error: output port expression must support contiuous assignment.
port .a of module is connected to output1.

This repeats for all inputs... The error is pointing out what is true, I am literally connecting the output of the module to the input (hopefully for the next initiation), but not sure why it's an error in this way?

EDIT:::
Worked out that the outputs need to be the wires, and the new inputs are the registers! Many thanks for your help! One final problem... ack is set as a wire, I need to at the end of the 16 run throughs, set it to 1, in order to stop the thing.

 

[FvM]

If you need to use the module as is, there's no other option than instantiating it outside the sequential code and connect it through wires and registers, as suggested.

But apparently, the module contains only combinational code, otherwise it would need a clock input. In this case, it can be rewritten as a function and "called" from sequential code.