aymanzizo
Newbie level 1
hello every one,,,
i face a problem during veriloga simulation.
when i make veriloga models,i succeed in creating symbols for them
and simulating them in another schematic making the view list starting with veriloga
but the problem is when i make a schematic for some of veriloga models and create a top symbol for these veriloga symbols after creating pins,i can't do any simulation on the top symbol.
for example : if i want to make a divide by 2 circuit,i build up latches and gates by veriloga then connect them in a new schematic and then i want to make only one symbol for the whole circuit.
the icfb window gives me that no netlist have been created
what can i do now
i face a problem during veriloga simulation.
when i make veriloga models,i succeed in creating symbols for them
and simulating them in another schematic making the view list starting with veriloga
but the problem is when i make a schematic for some of veriloga models and create a top symbol for these veriloga symbols after creating pins,i can't do any simulation on the top symbol.
for example : if i want to make a divide by 2 circuit,i build up latches and gates by veriloga then connect them in a new schematic and then i want to make only one symbol for the whole circuit.
the icfb window gives me that no netlist have been created
what can i do now
