VerilogA module in Spectre: access to outside data

[IADanilov]

Hello!
I write VerilogA module which must work together with BSIM model (also written by VerilogA) to obtain advanced facilities in comparison with standart BSIM.

In this case transistor instance is implemented by subcircuit (inline subckt ...) which include two VerilogA modules: BSIM model and my module.

My module must obtain instance name (which is implemented by subcircuit). How can I do this?

Thanks.

 

[dick_freebird]

Why do you need the name?

I've been writing veriloga "wrappers" to implement things
like SOI "kink" behaviors, and just pass the S, D, G signals
through the "wrapper" to the foundry FET model.

I suspect there may be $ functions (like I am using $table_model
to populate the drain conductance response map) that give
you system-level access and maybe argument values.

If the subcircuit generates the instance name then that name
can also be passed as an argument to your veriloga instance,
no? I am passing Analog Environment user variables
in on the element card for the veriloga, seems like you could
do that with the generated name.

 

[IADanilov]

Each instance of my module must know the name of transistor in the netlist with which it is coupled.