Jun 21, 2006 #1 N nxing Advanced Member level 1 Joined May 10, 2004 Messages 421 Helped 25 Reputation 50 Reaction score 10 Trophy points 1,298 Location China Activity points 2,856 hello everyone, I am trying to write a opamp model with verilog-A, there is a model from ahdlLib, however, I want something diff in with diff out and now I am stucked to how to define the output stage with Common-mode voltage. Any suggestions? Regards,
hello everyone, I am trying to write a opamp model with verilog-A, there is a model from ahdlLib, however, I want something diff in with diff out and now I am stucked to how to define the output stage with Common-mode voltage. Any suggestions? Regards,