Verilog While Loop Error in Synthesis

[omara007]

integer verilog loop

Hi folks

I'm currently having the following MUX Verilog code:

   input [29:0]  port0;
   input [29:0]  port1;
   input [29:0]  port2;
   input [29:0]  port3;
   input [29:0]  port4;
   input [29:0]  port5;
   input [29:0]  port6;
   input [29:0]  port7;

   reg [7:0]	sel;

   reg [29:0]  mux8to1;         //Multiplexer 8 to 1  

always @ (in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7 or sel)
     casex( sel )
       8'bxxxxxxx1: mux8to1	= port0;		// port0 selected
       8'bxxxxxx10: mux8to1	= port1;		// port1 selected
       8'bxxxxx100: mux8to1	= port2;		// port2 selected
       8'bxxxx1000: mux8to1	= port3;		// port3 selected
       8'bxxx10000: mux8to1	= port4;		// port4 selected
       8'bxx100000: mux8to1	= port5;		// port5 selected
       8'bx1000000: mux8to1	= port6;		// port6 selected
       8'b10000000: mux8to1	= port7;		// port7 selected
       default:     uumux32to1sp	= 0;
     endcase

I was asked to convert this code so as to be of a generic number of input ports instead of being fixed to 8 ports. The new range of ports is from 1 to 8 ports.

Here is my new code:

   input [(30*`NUMBER_OF_PORTS)-1:0] portx;    
   reg [NUMBER_OF_PORTS-1:0]	sel;
   reg [29:0]  mux8to1;         

   integer index;

   always @ (portx or sel) begin
      index = 0;
      while (sel[index] == 0) begin
            index = index + 1;
      end
      mux8to1 = portx[(index*30)+29:(index*30)];
   end

The problem appeared when I tried to synthesize the code using Synplify. I got the following error regarding the loop:

 Range bounds are not constant.

and it pointed to the "index" integer in this statement:

   mux8to1 = portx[(index*30)+29:(index*30)];

So, what could be the problem here ? .. and if there is a problem about using an integer .. or a synthesizable while loop .. please advise regarding a different approach to parametrize this code ..

 

[dcreddy1980]

verilog parameter for loop synthesizable

u have declared integer index;

Index is not constant and it does know the limit for the index, If you convert the integer index; --> reg [5:0] index some thing like this then the tool will be able to build a hardware and knows the exact the limit of index.

 

[omara007]

verilog loop parameter synthesis

u have declared integer index;

Index is not constant and it does know the limit for the index, If you convert the integer index; --> reg [5:0] index some thing like this then the tool will be able to build a hardware and knows the exact the limit of index.

I changed the code to the following:

   reg [2:0] index;

   always @ (portx or sel or index) begin
      index = 3'b0;
      while (sel[index] == 1'b0) begin
            index = index + 1;
      end
      mux8to1 = portx[(index*30)+29:(index*30)];
   end

Besides changing the integer to reg of size 3, I also discovered that I wasn't including the "index" in the sensitivity list. I have effectively included it this time. Yet, I'm still receiving the same synthesis error : Range bounds are not constant .. and also pointing to the same line of code after modification.

 

[j_andr]

/.../

may by this hepls ?

module xyz
(
  input       [NrOfPorts_Width-1:0]   sel,
  input       [Width*NrOfPorts-1:0]   portx,
  output  reg [Width-1 :0]            ux8to1
);

parameter  NrOfPorts_Width = 2,
           NrOfPorts       = 2**NrOfPorts_Width,
           Width           = 4;

integer i;

always @(sel,portx)
  for  ( i = 0; i < Width; i = i+1 )
    begin
       ux8to1[i] <= portx[i+(sel*Width)];
    end
endmodule

the point is you can not use anything except constans when
defining vector ranges x[a:b];
the above is a kind of work-around, may be there is a better
way to do it, I've found such way only;
---

 

[dcreddy1980]

I completely agree with j_andr, he is right about the vector ranges, I simply forgot about it and thinking about the while loop

 

[omara007]

/.../

may by this hepls ?

module xyz
(
  input       [NrOfPorts_Width-1:0]   sel,
  input       [Width*NrOfPorts-1:0]   portx,
  output  reg [Width-1 :0]            ux8to1
);

parameter  NrOfPorts_Width = 2,
           NrOfPorts       = 2**NrOfPorts_Width,
           Width           = 4;

integer i;

always @(sel,portx)
  for  ( i = 0; i < Width; i = i+1 )
    begin
       ux8to1[i] <= portx[i+(sel*Width)];
    end
endmodule

the point is you can not use anything except constans when
defining vector ranges x[a:b];
the above is a kind of work-around, may be there is a better
way to do it, I've found such way only;
---

This doesn't solve the problem. Please notice the "CASEX" ..

The "CASEX" here searches for the first occurrence of "1" in the selector signal (starting at LSB). The order of the first "1" in the selector signal will be the port number to be mapped to the MUX output. Did you notice this ?

 

[dcreddy1980]

module xyz 
( 
  input       [NrOfPorts_Width-1:0]   sel, 
  input       [Width*NrOfPorts-1:0]   portx, 
  output  reg [Width-1 :0]            ux8to1 
); 

parameter  NrOfPorts_Width = 2, 
           NrOfPorts       = 2**NrOfPorts_Width, 
           Width           = 4; 

integer i,j; 
reg [NrOfPorts_Width-1:0] sel_tmp;
reg enable;

always@(*)
begin
 for(j=0;j<NrOfPorts_Width;j=j+1)
  begin
   if(sel[j] == 1'b1) begin
    sel_tmp <= j;
    enable <= 1'b1;
   end
   else begin
    sel_tmp <= 0;
    enable <= 1'b0;
   end
  end
end

always @(*) 
  for  ( i = 0; i < Width; i = i+1 ) 
    begin 
       ux8to1[i] <= portx[i+(sel*Width)] & {width{enable}}; 
    end 
endmodule

I have added additional functionality to j_andr code, how about this??

 

[j_andr]

/.../Did you notice this ?

honestly I did not, but seems to me your main problem was:
Range bounds are not constant;
as you have a solution of this error modification of my
example should easy;
---

 

[omara007]

dcreddy1980 .. Would you please explain the functionality of the added (enable) signal ? ..

Added after 2 minutes:

/.../Did you notice this ?

honestly I did not, but seems to me your main problem was:
Range bounds are not constant;
as you have a solution of this error modification of my
example should easy;
---

Thanks anyhow .. but I'm still unable to combine your approach with mine to get a synthesizable code that implements the same functionality

 

[dcreddy1980]

I just made enable signal so that i dont get any latch inference, if you are fine with latch inference, u can just remove enable logic generation