hMirkiXestra
Newbie level 5
Hello all!
I ve been synthesizing a RTL VHDL model in Synopsys and i ve been
using the block commands in VHDL:
<block name>:block
begin
....<code here>
....
....
end
and with the directive of DC group_hdl_block, i could group some pieces together and
observe their functionailty.
Anyone knows how to do that in Verilog???
Regards.
I ve been synthesizing a RTL VHDL model in Synopsys and i ve been
using the block commands in VHDL:
<block name>:block
begin
....<code here>
....
....
end
and with the directive of DC group_hdl_block, i could group some pieces together and
observe their functionailty.
Anyone knows how to do that in Verilog???
Regards.
