Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[verilog] trigger selection of rising and falling edge

Status
Not open for further replies.

gunkaragoz

Newbie level 1
Joined
May 10, 2010
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Izmir Institute of Technology
Activity points
1,286
hi. now i'm trying to realize a digital backend for a 200 msps data acquisition system with verilog. actually this is the digital part of a digital storage oscilloscope.

i have a problem with trigger module. i want trigger mode(posedge or negedge) to be selected. but as i know i cannot use if statement before always block. how can i do the selection?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top