[SOLVED] verilog to vhdl translation

[femystika08]

Hi,
I recently translated a code from verilog to vhdl and got some syntax errors.
verilog code

`timescale 1ns/10ps
module dct_mac(
              clk, 
				  ena, 
				  dclr, 
				  din, 
				  coef, 
				  result
				  );
				  

parameter dwidth = 8;
parameter cwidth = 16;
parameter mwidth = dwidth + cwidth;  
parameter rwidth = mwidth +3;        

input               clk;    
input               ena;    
input               dclr;   
input  [dwidth-1:0] din;   
input  [cwidth-1:0] coef;  
output [rwidth-1:0] result; 
reg [rwidth -1:0] result;

wire [mwidth-1:0] idin;
wire [mwidth-1:0] icoef;

reg  [mwidth -1:0] mult_res ;
wire [rwidth -1:0] ext_mult_res;


assign icoef = { {(mwidth-cwidth){coef[cwidth-1]}}, coef};
assign idin  = { {(mwidth-dwidth){din[dwidth-1]}}, din};

always @(posedge clk)
begin
	  if(ena)
	  mult_res<=icoef * idin; 
end

assign ext_mult_res = { {3{mult_res[mwidth-1]}}, mult_res};


always @(posedge clk)
begin
	  if(ena)
	  begin
	        if(dclr)
	        result<=ext_mult_res;
	    else
	        result<=ext_mult_res + result; 
	  end
end			
endmodule

vhdl code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
--use ieee.std_logic_arith.all;
entity dct_mac is 
generic (
        dwidth : INTEGER := 8 ;
        cwidth : INTEGER := 16 ;
        mwidth : INTEGER := 24 ;
        rwidth : INTEGER := 27 
    );
     port (
        clk :  in std_logic;
        ena :  in std_logic;
        dclr :  in std_logic;
        din :  in std_logic_vector( ( dwidth - 1  )  downto 0  );
        coef :  in std_logic_vector( ( cwidth - 1  )  downto 0  );
        result :  out std_logic_vector( ( rwidth - 1  )  downto 0  )
    );
end dct_mac; 


architecture rtl of dct_mac is 
    signal idin : std_logic_vector( ( mwidth - 1  )  downto 0  );
    signal icoef : std_logic_vector( ( mwidth - 1  )  downto 0  );
    signal mult_res : std_logic_vector( ( mwidth - 1  )  downto 0  );
    signal ext_mult_res : std_logic_vector( ( rwidth - 1  )  downto 0  );
    begin 
        icoef <= ( ( coef(( cwidth - 1  ) ) & coef(( cwidth - 1  ) ) & coef(( cwidth - 1  ) ) & coef(( cwidth - 1  ) ) & coef(( cwidth - 1  ) ) & coef(( cwidth - 1  ) ) & coef(( cwidth - 1  ) ) & coef(( cwidth - 1  ) ) ) & coef );
        idin <= ( ( din(( dwidth - 1  ) ) & din(( dwidth - 1  ) ) & din(( dwidth - 1  ) ) & din(( dwidth - 1  ) ) & din(( dwidth - 1  ) ) & din(( dwidth - 1  ) ) & din(( dwidth - 1  ) ) & din(( dwidth - 1  ) ) & din(( dwidth - 1  ) ) & din(( dwidth - 1  ) ) & din(( dwidth - 1  ) ) & din(( dwidth - 1  ) ) & din(( dwidth - 1  ) ) & din(( dwidth - 1  ) ) & din(( dwidth - 1  ) ) & din(( dwidth - 1  ) ) ) & din );
        process 
        begin
            wait until ( clk'EVENT and ( clk = '1' )  ) ;
            if ( ena = '1' ) then 
                mult_res <= ( icoef * idin) ; -- error
            end if;
        end process;
        ext_mult_res <= ( ( mult_res(( mwidth - 1  ) ) & mult_res(( mwidth - 1  ) ) & mult_res(( mwidth - 1  ) ) ) & mult_res );
        process 
        begin
            wait until ( clk'EVENT and ( clk = '1' )  ) ;
            if ( ena = '1' ) then 
                if ( dclr = '1' ) then 
                    result <= ext_mult_res;
                else 
                    result <= ( ext_mult_res + result) ; -- error
                end if;
            end if;
        end process;
    end rtl;

I get these errors when I run the vhdl code

Line 66. * can not have such operands in this context.
Line 77. + can not have such operands in this context.

I don't understand why arithmetic operations are not allowed here.
Thanks in advance for any suggestions.

 

[sherif123]

You should use
use ieee.std_logic_unsigned.all;
This allows you to apply math operators on std_logic_vectors

or
you convert std_logic_vector to unsigned then apply math operator then convert back to std_logic_vector
ex.
mult_res <= std_logic_vector( unsigned(icoef) * unsigned(idin))

refer to
https://cdstahl.org/?p=761

I see that u already know that this line is error
result <= ( ext_mult_res + result) ; -- error

In case that u don't know the reason, you should know that outputs can't be read in vhdl. You should first define a new signal ex sResult and work with however u want then assign it later outside the process to the output

if ( ena = '1' ) then
if ( dclr = '1' ) then
result <= ext_mult_res;
else
result <= ( ext_mult_res + result) ; -- error
end if;
end if;

should be converted to

if ( ena = '1' ) then
if ( dclr = '1' ) then
sresult <= ext_mult_res;
else
sresult <= ( ext_mult_res + sresult) ; -- error
end if;
end if;
result <= sresult;