brunokasimin
Member level 4
verilog to vhdl translator
hello,
here is my small verilog code:
sel_ram <= op and (wb_i_adr[31:30] == 2'b11);
sel_rom <= op and (wb_i_adr[31:30] == 2'b00);
sel_io <= op and (wb_i_adr[31:30] == 2'b01);
and i translated into vhdl:
if wb_i_adr(31 downto 0)= "11" then
sel_ram <= op and "11";
if wb_i_adr(31 downto 0)= "00" then
sel_rom <= op and "00";
if wb_i_adr(31 downto 0)= "01" then
sel_io <= op and "01";
is there any error on the translation?? comments are really appreciated
thx in advanced
bruno
hello,
here is my small verilog code:
sel_ram <= op and (wb_i_adr[31:30] == 2'b11);
sel_rom <= op and (wb_i_adr[31:30] == 2'b00);
sel_io <= op and (wb_i_adr[31:30] == 2'b01);
and i translated into vhdl:
if wb_i_adr(31 downto 0)= "11" then
sel_ram <= op and "11";
if wb_i_adr(31 downto 0)= "00" then
sel_rom <= op and "00";
if wb_i_adr(31 downto 0)= "01" then
sel_io <= op and "01";
is there any error on the translation?? comments are really appreciated
thx in advanced
bruno