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Verilog testbench generator

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optimuz

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Hi,
Anyone knows any software or scripts which can generate a verilog testbench for a Verilog design.

I am not looking for a tbgen which uses dumb files. But a testbench to do a RTL Vs Netlist simulation.
Where it can generate all input patters or combinations of corner cases and does a RTL - Netlist comparison.

You might have a suggestion of doing a formal verification with tools like Formality.
I cant use it because I am use some verilog constructs which Formality doesnt supports and my rtl is large were I cannot do a `ifdef synthesis approach.

Thanks,
Optimuz
 

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