Verilog Test-Bench Error When Simulate

Code Verilog - [expand]
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module circuit_c
    (
    input [2:0]a,
    input [2:0]b,
    output [3:0]out1,
    input [2:0]c,
    output [5:0]out2
    );
 
    assign out1={a,b};
    assign out2={3{c}};
endmodule
 
my Test-bench
 
module circuit_c_tb;
    reg [2:0]a_tb;
    reg [2:0]b_tb;
    wire [3:0]out1_tb;
    reg [2:0]c_tb;
    wire [5:0]out2_tb;
 
    initial begin
    $monitor("@%0d, a=%b, b=%b, c=%b, out1=%b, out2=%b",
        $time, a_tb, b_tb, c_tb, out1_tb, out2_tb);
    end
 
    circuit_c_tb myCircuitC(
        .a(a_tb),
        .b(b_tb),
        .c(c_tb),
        .out1(out1_tb),
        .out2(out2_tb)
        );
 
    initial begin
    a_tb = 2'b01;
    b_tb = 2'b01;
    c_tb = 2'b01;
    #1 b_tb = 2'b11;
    #1 a_tb = 2'b11;
    #1 c_tb = 2'b10;
    a_tb = 2'b00;
    #1;
    end
endmodule