C , VERILOG, VHDL.

[blarsen]

I'm new to Verilog. I'm reading "A Verilog HDL Primer" by Bhasker along with other Verilog description sources. I have a question about tasks, functions, and modules. Why would you use a task or function within a module instead of just writing Verilog in a module
and then instantiate the module? I hope my question is clear. Thanks.

 

[rajavel.rv]

refer this link : https://www.lsi.upc.edu/~jordicf/Teaching/secretsofhardware/VerilogIntroduction_Nyasulu.pdf

regards
rajavel.rv

 

[gs65]

hi,
tasks and functions are like activities which are to be performed repeatedly. instead of writing code for them again and again, write a seperate code for it and call them whenever necessary any no.of times