wisemonkey
Junior Member level 3
Hi,
I'm working on IP core project. so I need few configurable inputs and few user inputs.
I'm using `ifdef and `endif mostly to have different designs and I know (as much as I can remember) those can be used for synthesis as well without any issue if `ifdef-`endif used correctly.
However my issue is, Does SV or Verilog have facility to take user inputs? I want to take width of a signal as an input.
And how to use math functions in SV / Verilog. I want to use log2(number) function or even better I want to see if number is a power of 2 if not then find out immediate power of 2 (I'm interested in power only)
P.S. All these values will be assigned to variables before compilation so I won't call them dynamic as such, however they need to be configurable (in sense of MUX) and one user input.
Thanks
I'm working on IP core project. so I need few configurable inputs and few user inputs.
I'm using `ifdef and `endif mostly to have different designs and I know (as much as I can remember) those can be used for synthesis as well without any issue if `ifdef-`endif used correctly.
However my issue is, Does SV or Verilog have facility to take user inputs? I want to take width of a signal as an input.
And how to use math functions in SV / Verilog. I want to use log2(number) function or even better I want to see if number is a power of 2 if not then find out immediate power of 2 (I'm interested in power only)
P.S. All these values will be assigned to variables before compilation so I won't call them dynamic as such, however they need to be configurable (in sense of MUX) and one user input.
Thanks