shaiko
Advanced Member level 5
Hello,
VHDL supports leaving the size of component ports unconstrained during declaration.
Unconstrained ports are constrained during elaboration by inheriting the sizes of the signals we connect to them.
Example:
Questions:
1. Does Verilog support this?
2. Does System Verilog support this?
VHDL supports leaving the size of component ports unconstrained during declaration.
Unconstrained ports are constrained during elaboration by inheriting the sizes of the signals we connect to them.
Example:
Code:
signal some_signal : std_logic_vector ( 7 downto 0 ) ;
instantiation_of_some_entity : some_entity
(
some_port => some_signal
) ;
--some_entity could have been declared as:
entity some_entity is
port
(
some_port : std_logic_vector ( 7 downto 0 ) ; some_port is constrained
) ;
end entity some_entity ;
--some_entity could have also been declared as:
entity some_entity is
port
(
some_port : std_logic_vector -- some_port is unconstrained
) ;
end entity some_entity ;Questions:
1. Does Verilog support this?
2. Does System Verilog support this?