HansD
Newbie level 1
Verilog synthesis problem "BLOCK RAM inferencing failed, output is not synchronous."
Hello. I'm currently designing a single-cycle MIPS processor in Verilog, and was trying to synthesize the Data Memory module on a Spartan FPGA using Altium Synthesizer. However, I have a synthesis error that says:
"BLOCK RAM inferencing failed, output is not synchronous (!inst_driven)."
My code is as follows:
What the Data Memory is supposed to do is act as a combinational memory when read (that is, if the address changes the rD output changes), but should only write synchronously when WE is 1. Anyone knows what might be the problem and how to solve it? I would greatly appreciate any help!
Hello. I'm currently designing a single-cycle MIPS processor in Verilog, and was trying to synthesize the Data Memory module on a Spartan FPGA using Altium Synthesizer. However, I have a synthesis error that says:
"BLOCK RAM inferencing failed, output is not synchronous (!inst_driven)."
My code is as follows:
Code:
module DataMem(CLK, WE, A, wD, rD);
input wire CLK, WE;
input wire [31:0] A;
input wire [31:0] wD;
output wire [31:0] rD;
reg [31:0] memory[63:0];
assign rD = memory[A];
always @(posedge CLK)
if(WE) memory[A] <= wD;
endmodule
What the Data Memory is supposed to do is act as a combinational memory when read (that is, if the address changes the rD output changes), but should only write synchronously when WE is 1. Anyone knows what might be the problem and how to solve it? I would greatly appreciate any help!