Verilog synthesis problem "BLOCK RAM inferencing failed, output is not synchronous."

[HansD]

Verilog synthesis problem "BLOCK RAM inferencing failed, output is not synchronous."

Hello. I'm currently designing a single-cycle MIPS processor in Verilog, and was trying to synthesize the Data Memory module on a Spartan FPGA using Altium Synthesizer. However, I have a synthesis error that says:

"BLOCK RAM inferencing failed, output is not synchronous (!inst_driven)."

My code is as follows:

module DataMem(CLK, WE, A, wD, rD);
input wire CLK, WE;
input wire [31:0] A;
input wire [31:0] wD;
output wire [31:0] rD;
reg [31:0] memory[63:0];

assign rD = memory[A];

always @(posedge CLK)
    if(WE) memory[A] <= wD;

endmodule

What the Data Memory is supposed to do is act as a combinational memory when read (that is, if the address changes the rD output changes), but should only write synchronously when WE is 1. Anyone knows what might be the problem and how to solve it? I would greatly appreciate any help!

 

[atulaxc]

Re: Verilog synthesis problem "BLOCK RAM inferencing failed, output is not synchronou

I think what you are trying is to implement is a single port memory without proper control mechanism for reads. Synthesis tools fails, when they can't map the design to exiting library. Try adding rd control signals. You can refer Verilog code for the memory from following link Verilog memory code. Synchronous Random Access Memory (RAM). Testbench memory modeling.

 

[FvM]

Re: Verilog synthesis problem "BLOCK RAM inferencing failed, output is not synchronou

I think what you are trying is to implement is a single port memory without proper control mechanism for reads. Synthesis tools fails, when they can't map the design to exiting library. Try adding rd control signals.

The problem is not caused by missing controld signals rather than the fact, that A isn't registered when reading the RAM asynchronously.

assign rD = memory[A];

The error message is pointing to the problem exactly: "output is not synchronous"

The below code can work

always @(posedge CLK)
  begin
    if(WE) memory[A] <= wD;
    rD = memory[A];
  end