Oct 4, 2011 #1 F farklempt Newbie level 4 Joined Oct 4, 2011 Messages 6 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,321 What does -: and +: mean inside a vector definition such as: data[32 -:8] data[32 +:8]
Oct 4, 2011 #2 J j_andr Full Member level 4 Joined Mar 30, 2008 Messages 207 Helped 59 Reputation 118 Reaction score 37 Trophy points 1,308 Location europe Activity points 2,491 data[32 -:8] -> data[32 : 25] 8 bits starting from bit nr. 32 DOWN data[32 +:8] -> data[32 : 39] - " - UP
data[32 -:8] -> data[32 : 25] 8 bits starting from bit nr. 32 DOWN data[32 +:8] -> data[32 : 39] - " - UP
Oct 4, 2011 #3 F farklempt Newbie level 4 Joined Oct 4, 2011 Messages 6 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,321 Thanks! Nice explanation.
Oct 12, 2011 #4 Q qieda Full Member level 3 Joined Aug 15, 2006 Messages 150 Helped 47 Reputation 94 Reaction score 47 Trophy points 1,308 Activity points 2,174 maybe I'm wrong but I think data[32 +:8] does give data[39 : 32] not data[32 : 39] at least when data was defined as reg [39:0] data; regards
maybe I'm wrong but I think data[32 +:8] does give data[39 : 32] not data[32 : 39] at least when data was defined as reg [39:0] data; regards
Oct 12, 2011 #5 J j_andr Full Member level 4 Joined Mar 30, 2008 Messages 207 Helped 59 Reputation 118 Reaction score 37 Trophy points 1,308 Location europe Activity points 2,491 qieda said: maybe I'm wrong but I think data[32 +:8] does give data[39 : 32] not data[32 : 39] at least when data was defined as reg [39:0] data; Click to expand... you are right, my mistake; J.A
qieda said: maybe I'm wrong but I think data[32 +:8] does give data[39 : 32] not data[32 : 39] at least when data was defined as reg [39:0] data; Click to expand... you are right, my mistake; J.A
Oct 12, 2011 #6 FvM Super Moderator Staff member Joined Jan 22, 2008 Messages 52,472 Helped 14,756 Reputation 29,794 Reaction score 14,119 Trophy points 1,393 Location Bochum, Germany Activity points 298,317 but I think data[32 +:8] does give data[39 : 32] not data[32 : 39] at least when data was defined as reg [39:0] data; Click to expand... It's wrong. Why don't you refer to the Verilog specification, it has clear examples for indexed part select syntax (in IEEE Std 1364-2005, 5.2.1 Vector bit-select and part-select addressing): Code: big_vect[ 0 +: 8] // == big_vect[ 7 : 0] big_vect[15 -: 8] // == big_vect[15 : 8] little_vect[ 0 +: 8] // == little_vect[0 : 7] little_vect[15 -: 8] // == little_vect[8 :15] You see that +: always involves index numbers above the start value.
but I think data[32 +:8] does give data[39 : 32] not data[32 : 39] at least when data was defined as reg [39:0] data; Click to expand... It's wrong. Why don't you refer to the Verilog specification, it has clear examples for indexed part select syntax (in IEEE Std 1364-2005, 5.2.1 Vector bit-select and part-select addressing): Code: big_vect[ 0 +: 8] // == big_vect[ 7 : 0] big_vect[15 -: 8] // == big_vect[15 : 8] little_vect[ 0 +: 8] // == little_vect[0 : 7] little_vect[15 -: 8] // == little_vect[8 :15] You see that +: always involves index numbers above the start value.
Oct 12, 2011 #7 mrflibble Advanced Member level 5 Joined Apr 19, 2010 Messages 2,720 Helped 679 Reputation 1,360 Reaction score 652 Trophy points 1,393 Activity points 19,551 Had to look up the declaration of big_vect and little_vect... Code: reg [15:0] big_vect; reg [0:15] little_vect; big_vect[ 0 +: 8] // == big_vect[ 7 : 0] big_vect[15 -: 8] // == big_vect[15 : 8] little_vect[ 0 +: 8] // == little_vect[0 : 7] little_vect[15 -: 8] // == little_vect[8 :15]
Had to look up the declaration of big_vect and little_vect... Code: reg [15:0] big_vect; reg [0:15] little_vect; big_vect[ 0 +: 8] // == big_vect[ 7 : 0] big_vect[15 -: 8] // == big_vect[15 : 8] little_vect[ 0 +: 8] // == little_vect[0 : 7] little_vect[15 -: 8] // == little_vect[8 :15]