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`timescale 1ps / 1ps       // do not change
 
module fsl_ddr_eye_ctl (
   output ck,
   output addr_cmd,
   output ctl,
   output dm,
   inout dq,
   inout dqs
);
 
 
/****************************************************************************************
*  Default values, in case something slips through undefined...
****************************************************************************************/
`ifndef tCK
   `define tCK 1250
`endif
   parameter tDQBit = `tCK / 2;                 // Data bit time
 
 
// Comment the following to use the "approximate" method
`define USE_EXACT_VALUES
 
   // translated values (approx)          // datasheet values 
   parameter tDDKHMH =  (tDQBit < 580) ? 150 : (tDQBit < 688) ? 150 : (tDQBit < 791) ? 245 ;   // straight from datasheet...
 
`ifdef USE_EXACT_VALUES
   parameter tCISKEW   =  (tDQBit < 580) ?  93 : (tDQBit < 688) ? 112 : (tDQBit < 791) ? 125 ;   
   parameter tDDKHAS   =  (tDQBit < 580) ? 410 : (tDQBit < 688) ? 495 : (tDQBit < 791) ? 606 ; 
   parameter tDDKXDEYE =  (tDQBit < 580) ? 350 : (tDQBit < 688) ? 400 : (tDQBit < 791) ? 500 ; 
 
`else
   parameter tCISKEW   = 0.1800 * tDQBit;     // @1333= 125
   parameter tDDKHAS   = 0.3900 * `tCK;       // @1333= 606
   parameter tDDKXDEYE = 0.6667 * tDQBit;     // @1333= 500
`endif
 
 
 
   integer CLK_ADJ = 10;
   integer CNTL_ADJ = 0;
   integer WR_DATA_DLY = 0;
 
 
/****************************************************************************************
*  Derived timing parameters
****************************************************************************************/
   parameter tACCSkew = `tCK/2 - tDDKHAS;       // The raw tDDKHAS term assumes 1/2 tCK nominal shift
   parameter tACCShift = CLK_ADJ * `tCK/16;      // Base Addr/Cmd/Ctl to CK delay
   parameter tACCDlyMin = -tACCShift - tACCSkew;   // Delay from CK rising to Addr/Cmd/Ctl valid (min)
   parameter tACCDlyMax = -tACCShift + tACCSkew;   // Delay from CK rising to Addr/Cmd/Ctl valid (max)
 
   parameter tCKCTLmin = tACCDlyMin;            // CK rising out to earliest valid CTL (CK-1)
   parameter tCKCTLmax = tACCDlyMax;            // CK rising out to latest valid CTL (CK-1)
`ifdef ADDRCMD2T
   parameter tCKACmin = tACCDlyMin - `tCK;      // CK rising out to earliest valid Addr/Cmd (CK-2)
   parameter tCKACmax = tACCDlyMax - `tCK;      // CK rising out to latest valid Addr/Cmd (CK-2)
`else `define ADDRCMD1T
   parameter tCKACmin = tACCDlyMin;             // CK rising out to earliest valid Addr/Cmd (CK-1)
   parameter tCKACmax = tACCDlyMax;             // CK rising out to latest valid Addr/Cmd (CK-1)
`endif
 
   parameter tDQPrelaunch = -tDQBit/2;          // DQ to DQS pre-launch shift (Write to DRAM)
   parameter tDQSDQQ = tDQBit/2 - tDDKXDEYE/2;  // DQ output skew, relative to DQS
   parameter tDQSDQmin = tDQPrelaunch - tDQSDQQ;
   parameter tDQSDQmax = tDQPrelaunch + tDQSDQQ;
   parameter tDQSShift = WR_DATA_DLY * `tCK/4;  // Base Addr/Cmd/Ctl to DQS delay (write)
   parameter tDQSDly = tDQSShift - tACCShift;   // Base CK to DQS delay (write)
   parameter tCKDQSmin = tDQSDly - tDDKHMH;
   parameter tCKDQSmax = tDQSDly + tDDKHMH;
   parameter tDISKEW = `tCK/4 - tCISKEW;
   parameter tDS = tCISKEW;
   parameter tDH = tCISKEW;
 
 
/****************************************************************************************
*  Timing relationships
****************************************************************************************/
specify
 
   // ADDR/CMD prelaunch window from next CK
   $delay( posedge ck, addr_cmd, tCKACmin, tCKACmax);
   // CTL prelaunch window from next CK (1T always)
   $delay( posedge ck, ctl, tCKCTLmin, tCKCTLmax);
 
   // DRAM Write cycles
   $delay(ck, dqs, tCKDQSmin, tCKDQSmax);
   $delay(dqs, dq, tDQSDQmin, tDQSDQmax);
   $delay(dqs, dm, tDQSDQmin, tDQSDQmax);
 
   // DRAM Read cycles
   $setuphold(dqs, dq, tDS, tDH);
 
endspecify
 
endmodule