verilog syntax error near "reg" execting a direction

[Luchete 1]

Hi, i'm learning about verilog and recently bought a max II CPLD kit, i was doing a verilog program trying to make a 7 segment display go form 0 to f on hex in a 1s delay (max II internal clk is 50MHz) between digits. i can't find the error in the syntaxis in that part of the code

Error (10170): Verilog HDL syntax error at Hex_7seg.v(3) near text: "reg"; expecting a direction.

module Hex_7seg(
    input clk,
    reg sig,
    reg [6:0] seg_data,
    output [6:0] seg
);

 reg [25:0] contador;
 reg [3:0] hex = 4'h0;

always @(posedge clk) begin
     if (contador == 25000000)
     begin
        contador <= 0;
        sig <= ~sig;
     end
     else begin
        contador <= contador + 1;
    end
end

//primer bloque me da en sig un clk de 1Hz

always @(negedge sig) begin
    case (hex)
        4'h0: seg_data = 7'b1000000; // 0
        4'h1: seg_data = 7'b1111001; // 1
        4'h2: seg_data = 7'b0100100; // 2
        4'h3: seg_data = 7'b0110000; // 3
        4'h4: seg_data = 7'b0011001; // 4
        4'h5: seg_data = 7'b0010010; // 5
        4'h6: seg_data = 7'b0000010; // 6
        4'h7: seg_data = 7'b1111000; // 7
        4'h8: seg_data = 7'b0000000; // 8
        4'h9: seg_data = 7'b0011000; // 9
        4'ha: seg_data = 7'b0001000; // A
        4'hb: seg_data = 7'b0000011; // B
        4'hc: seg_data = 7'b1000110; // C
        4'hd: seg_data = 7'b0100001; // D
        4'he: seg_data = 7'b0000110; // E
        4'hf: seg_data = 7'b0001110; // F
        default : seg_data = 7'b1110110; // U en caso de error
    endcase
    if (hex == 4'hf)
        begin
        hex <= 4'h0;
        end
    else
        begin
        hex <= hex +1;
        end
end
seg <= seg_data;

endmodule

 

[FvM]

Direction means inout, input or output. Required for each port declaration.

 

[dave_59]

Verilog does not allow the reg datatype applied to an input port. SystemVerilog would allow this. You can remove the reg keyword

 

[FvM]

Right, the queried ports are however undelared outputs. Must be declared as output reg.