[SOLVED] Verilog simulation question

[ammar_kurd]

Say I have number of modules (mod0(x,y), mod1(x,y), mod2(x,y), ...) can I instantiate those modules in the test-bench by using a for loop?

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Code Verilog - [expand]
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for (i = 0; i < n; i = i+1; )
//    here instantiate modules by somehow constructing the module name (mod+i) and an instance of
//    the module.
end

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I that possible?

 

[FvM]

Modules can be instantiated in a generate loop, but not in a sequential block, e.g. for loop. Review Verilog language reference manual.

The generate loop syntax is different from the above shown code.

 

[ammar_kurd]

OK I got you, but I have not one module that I want to instantiate but a number of modules, at iteration one I want to instantiate mod1 at two mod2, ...

How can I construct the module name "adding 1,2,..." at the end inside the loop? some sort of concatenation.

 

[FvM]

You can't manipulate identifiers in Verilog code. There's are very restricted options to achieve it with text macros. If n isn't a very large number, you'll succeed faster by instantiating the different modules explicitly.