Verilog - Simulation of Oscillator

[dshoter13]

Hi, I'm new to verilog and i'm trying to validate the theory behind a oscillator for TDC purporse.

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Code Verilog - [expand]
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//Verilog-AMS HDL for "ADPLL", "work_tb" "verilogams"
 
`timescale 1ns/1ps
`include "constants.vams"
`include "disciplines.vams"
 
module sgro (con1, vs1, vs2, vs3, vs4, vs5);
 
    input con1;
    output vs1, vs2, vs3, vs4, vs5;
    reg vs1, vs2, vs3, vs4, vs5;
    wire con1;
 
    initial begin
        
        vs1 = 0;
        vs2 = 0;
        vs3 = 0;
        vs4 = 0;
        vs5 = 0;
 
    end
 
    always @(con1) begin
            while(con1 == 1) begin
            if(con1 == 1) #5.6 vs1 = ~vs5;
            if(con1 == 1) #5.6 vs2 = ~vs1;
            if(con1 == 1) #5.6 vs3 = ~vs2;
            if(con1 == 1) #5.6 vs4 = ~vs3;
            if(con1 == 1) #5.6 vs5 = ~vs4;
            end
 
    end
 
endmodule

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My goal is to simulate the oscillator (ring topology) for the following scenarios:
- I want it to oscillate when the signal con1 is enable;
- As soon as the signal con1 becames 0, i want it to stop, freezing the state of each "output" (inverter)

Can anyone help me? I can make the oscillation happen, but when the signal con1 arrives, it does extra "oscillations" due to the While loop.
I'm completely new to verilog, so any help is welcome!

I'm sorry for my english.

Thank you all for your attention.

 

[sharath666]

Write your always block as below

always@(*)
begin
  if(con1 == 1'b1)
  begin
     #5.6 vs1 = ~vs5;
     #5.6 vs2 = ~vs1;
     #5.6 vs3 = ~vs2;
     #5.6 vs4 = ~vs3;
     #5.6 vs5 = ~vs4;
  end
  else
  begin
      vs1 = vs1;
      vs2 = vs2;
      vs3 = vs3;
      vs4 = vs4;
      vs5 = vs5;
  end
end

As you are new to HDL, I would recommend you to pickup some modules from the internet and learn about some basic verilog stuff like always blocks, registers, wires, loops etc..Only then think about writing a code

 

[dshoter13]

Write your always block as below

always@(*)
begin
  if(con1 == 1'b1)
  begin
     #5.6 vs1 = ~vs5;
     #5.6 vs2 = ~vs1;
     #5.6 vs3 = ~vs2;
     #5.6 vs4 = ~vs3;
     #5.6 vs5 = ~vs4;
  end
  else
  begin
      vs1 = vs1;
      vs2 = vs2;
      vs3 = vs3;
      vs4 = vs4;
      vs5 = vs5;
  end
end

As you are new to HDL, I would recommend you to pickup some modules from the internet and learn about some basic verilog stuff like always blocks, registers, wires, loops etc..Only then think about writing a code

Hi. Thank for you reply. I already saw some examples, and i already checked the basics .
I already tried that, but i'm using Cadence Virtuoso (verilog ams), and when i use if statements, the simulator just blocks.. it does not complete the simulation.. any suggestion?

Thank you.

 

[D.A.(Tony)Stewart]

but i'm using Cadence Virtuoso (verilog ams), and when i use if statements, the simulator just blocks

Verify syntax for verilog

if (index > 0) if (i > j)
result = i;
else // else applies to preceding if
result = j;

The conditional statement (or if-else statement) is used to make a decision as to whether a statement is executed or not. The syntax of a conditional statement is as follows:

conditional_statement ::=
if ( expression ) statement [ else statement ]

 

[dshoter13]

Write your always block as below

always@(*)
begin
  if(con1 == 1'b1)
  begin
     #5.6 vs1 = ~vs5;
     #5.6 vs2 = ~vs1;
     #5.6 vs3 = ~vs2;
     #5.6 vs4 = ~vs3;
     #5.6 vs5 = ~vs4;
  end
  else
  begin
      vs1 = vs1;
      vs2 = vs2;
      vs3 = vs3;
      vs4 = vs4;
      vs5 = vs5;
  end
end

As you are new to HDL, I would recommend you to pickup some modules from the internet and learn about some basic verilog stuff like always blocks, registers, wires, loops etc..Only then think about writing a code

I tried your solution, but for somo reason, the signal con1 stays equal to 1, but the statement inside if does not run... it only changes de states of regs vs1...vs5 once, then it freezes.
Any idea?


With best regards

- - - Updated - - -

I tried your solution, but for somo reason, the signal con1 stays equal to 1, but the statement inside if does not run... it only changes de states of regs vs1...vs5 once, then it freezes.
Any idea?


With best regards

Forget it, it works, I will test it better. Thanks

 

[dshoter13]

I pretend to simulate this kind of oscillator:

When i turn off the oscillator, i want the registers in my verilog code to stop changing theirs values. Anyone know how can i do this?

With best regards.

 

[FvM]

A three-state driver doesn't freeze a signal. It may keep if for a small time amount (e.g. 100 ns) with respective transistor capacitances, but Verilog isn't suited to model this behaviour because it's essentially analog hardware behaviour.

You might implement latches, the delay statements must be probably placed differently than in the post #2 code. You should clarify first if you want to model a specific hardware like FPGA or CPLD logic elements, ASIC gates or switch level, then make the hardware description accordingly.

 

[D.A.(Tony)Stewart]

I pretend to simulate this kind of oscillator:
View attachment 110664
When i turn off the oscillator, i want the registers in my verilog code to stop changing theirs values. Anyone know how can i do this?

With best regards.

• without bias R's, the clock output may be noisy when disabled as they are floating.
• rather than a tristate inverter, use a NAND gate in the loop to stop the clock.

 

[dshoter13]

A three-state driver doesn't freeze a signal. It may keep if for a small time amount (e.g. 100 ns) with respective transistor capacitances, but Verilog isn't suited to model this behaviour because it's essentially analog hardware behaviour.

You might implement latches, the delay statements must be probably placed differently than in the post #2 code. You should clarify first if you want to model a specific hardware like FPGA or CPLD logic elements, ASIC gates or switch level, then make the hardware description accordingly.

I pretend to simulate and validate the model of the GRO. After validation, i pretend to start the transistor level simulations.