Verilog simple but bit confusing

[balan]

Let me know the output of this program

module tb;
reg [15:0] a;
initial begin
a=28'hff00;
$display("a = %h",a);
$display("a = %0h",a);
$display("a = %7h",a);

end
endmodule

 

[balan]

whether the result which i get is expected.

1st display
ff00
2nd display
ff00
3rd display
ff00

Is that correct

 

[sheik_vb]

Yes Correct.

 

[balan]

The reg a is 16 bit, but the assignment is a = 28'h ff00 (assigned as 28 bit).

In the display we have given as $display("%7h",a)

I expect the value to be
000ff00.

Please let me know does %7h has any effect.

 

[tiger_cn]

There must be something wrong with your answer.
you can simular with modelsim and you can see de result are:

1st display
ff00
2nd display
ff
3rd display
___ff00 (_means Space bar)