verilog signed type conversion

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Alka Arora

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Hi ,

In VHDL we have a function to convert std_logic_vector to signed data type.Do we have anything like that in verilog to convert in to signed type in verilog.

for example i have wire [8:0] diff;

I want to convert it into absolute value.

Thanks
Alka
 

It's very easy for verilog.

Code: 
module abs_test(da_in,da_out);
input[8:0] da_in;
output[8:0] da_out;
assign da_out=(da_in[8])? (0-da_in):da_in;
endmodule
 

Thanks so much.I have a VHDL function 
Code VHDL - [expand]
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FUNCTION "-"   (L: STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
  BEGIN
    RETURN - SIGNED(L);
  END;
 
  FUNCTION "ABs" (L: STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
  BEGIN
    RETURN ABs (SIGNED(L));
  END;

I want to generate similiar logic in verilog but I am noot able to do that .

Thanks
Alka
 
Last edited by a moderator:

In Verilog, you can cast a signal to signed by using $signed function. e.g. $signed(diff).


 
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