Verilog shift opearor question

[bharath_kumar]

HI all ,

reg [7:0] y0 ;  // reg 
// r1 , g1 and b1 are 8 bit inputs.

assume r1 = 182 , g1 = 180 ; b1 = 183 ;

Case 1 : I used the code

yo <=  ( ( 7'd77*r0 )+( 8'd150*g0 )+( 5'd29*b0 ) ) >> 8	;

Case 2 : I used the code

y0  <= ( ( 7'd77*r0 )+( 8'd150*g0 )+( 5'd29*b0 ) ) / 256	;

In case (2) , i am getting the y0 180. ( this value is fine).

But in case (1) , i am getting 0 (zero) as out put.

I used the model SIM simulator.

Question : What is the problem with shift operator ???
Please answer me.



Best Regards
Bharath Kumar

 

[ads-ee]

Because the result requires 16-bits to fit before doing the >> operation.

Basically what is happening is the result of the multiplication and additions happens then the upper 8-bits are taken, except there aren't any upper 8-bits since y0a is only 8-bits. The / 256 does the division then assigns it so there is no need to keep track of the upper 8-bits.

1) use 16-bits for y0 and use only the upper 8-bits
2) use a 16-bit y0 and do the right shift and take only the lower 8-bits.

1 is the simplest to write.

 

[bharath_kumar]

Thanks ads ,

solution (1) , you mentioned is looking fine.


Best Regards
Bharath Kumar