Verilog Serial Demux

[Ajinkya Bobade]

i need some help for college hw which is as follows
Q) 1. Build a serial de-multiplexer unit in Verilog.  Inputs to the demux unit: Input clk, Input NewPacket, Input [7:0] DataIn
 Data comes in through the input port of variable length upto a maximum of 8 bytes. The Newpacket signal indicates arrival of new data packet during the current clock cyles. The first 4 bits(LSB) of DataIn during the first clock cycle indicates packet-size and the last 4 bits (MSB) indicates the initial output channel to select. The successive inputs are actual data packets that need to be routed. The output is routed starting from initial channel to successive output channels till the size of the packet.
 Output Signals, 8 output channels of 8 bits each: Output [7:0] DataOut0, DataOut1, DataOut2, DataOut3, DataOut4, DataOut5, DataOut6, DataOut7

Sample Input and output for the system is shown below
Clock: 0  10 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 
DataIn: 0 73 11  22  33  44  00  02  88  99 
NewPack: 0 1    0   0    0   0     0   1   0   0 
Dataout0: 0 00 00 00 22 00 00 00 00 88 00 00 
Dataout1: 0 00 00 00 00 33 00 00 00 00 99 00 
Dataout2: 0 00 00 00 00 00 00 00 00 00 00 00 
Dataout3: 0 00 00 00 00 00 00 00 00 00 00 00 
Dataout4: 0 00 00 00 00 00 00 00 00 00 00 00
Dataout5: 0 00 00 00 00 00 00 00 00 00 00 00 
Dataout6: 0 00 00 00 00 00 00 00 00 00 00 00
Dataout7: 0 00 00 11 00 00 00 00 00 00 00 00

i have done the following code:

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Code Verilog - [expand]
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module demux(DataIn,Initch,packsize,newpack,DataOut);
input  [7:0] DataIn;
output [7:0] DataOut;
input newpack;
 
//wiring all inputs
wire newpack;
reg[7:0] DataIn;
reg[7:0]DataOut;
 
always @(posedge clk)       // when positive edge is one 
begin:demux
if (newpack == 1'b1) begin   // when newpack is 1
 
  assign Initch=DataIn[4:7];
  assign Packsize=DataIn[0:3];
  assign active=1;
  assign CurrentCh=Initch;
    
 for (i=0; i<=7; i=i+1)  begin    // for next column to be zero as in figure1
   
      DataOut[i]= 0;
    
 end
  
 DataOut[CurrentCh]=DataIn;                                    
 CurrentCh=CurrentCh+1;
 end

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but its giving behavioural syntax error, please help

 

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It's pretty obvious you are trying to write Verilog code without even knowing anything about the language. You need to read at minimum a tutorial on basic syntax.
Here are the first three that show up on google.
http://www.ece.umd.edu/class/enee359a.S2008/verilog_tutorial.pdf
http://euler.ecs.umass.edu/ece232/pdf/03-verilog-11.pdf

Interesting observation is they are all from Universities, so maybe your university has one too?

Use 2001 port declarations avoids missing ports.

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Code Verilog - [expand]
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module demux(DataIn,Initch,packsize,newpack,DataOut);
input  [7:0] DataIn;
output [7:0] DataOut;
input newpack;

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would instead be:

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Code Verilog - [expand]
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module demux (
  input [7:0] DataIn,
  ?????   Initch, // based on later code is this an output?
  ?????   packsize, // based on later code is this an output?
  input   newpack,
  output reg [7:0] DataOut  // includes reg declaration in the port, don't need to repeat DataOut multiple times.
);

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Unnecessary and wrong stuff, you are also missing some required declarations for active and CurrentCh.

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Code Verilog - [expand]
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wire newpack; // unnecessary, wire is the default
reg[7:0] DataIn; // wrong can't do this, reg cannot be applied to an input port

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This is wrong too.

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always @(posedge clk)       // when positive edge is one 
begin:demux
if (newpack == 1'b1) begin   // when newpack is 1
 
// can't use assign inside a procedural block
  assign Initch=DataIn[4:7];
  assign Packsize=DataIn[0:3];
  assign active=1;
  assign CurrentCh=Initch;
// use non-blocking assignments in registered (FF) code
  Initch <= DataIn[4:7];
  Packsize <= DataIn[0:3];
  active <= 1;  // active is not declared, Verilog unless a compiler is informed otherwise will automatically create active VERY BAD CODING STYLE.
  CurrentCh <= Initch; // same problem as active.
 
// this is plain wrong, You are using the for loop for software code, it's not software it's for replication.
// this occurs instantly in 0 time and is therefore exactly the same as:
//   DataOut = 8'b0;
 for (i=0; i<=7; i=i+1)  begin    // for next column to be zero as in figure1
   
      DataOut[i]= 0;
    
 end
 
// this code will then reassign in the SAME CLOCK CYCLE the DataOout[CurrentCh] with DataIn,
// which means the previous assignment of DataOut = 8'b0; never happens.
 DataOut[CurrentCh]=DataIn; // should be non-blocking
 CurrentCh=CurrentCh+1; // shoudl be non-blocking
 end

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Never use blocking assignments (=) in edge triggered (clocked) code use non-blocking assginments (<=), which do emulated the behavior of a registers (FFs). Use blocking assignments only in combinational code.


You need to get and read a Verilog book your entire code is filled with numerous syntax errors and wrong thinking (software) of how to use Verilog.

Also you should know what the circuit described looks like in terms of FFs, logic, and pipeline before writing code. Otherwise it's much more difficult to write the description of the circuit in an HDL (Hardware Description Language).