Verilog reg and wire

[sun_ray]

Is there any drawback if a register variable in Verilog is assigned to an wire variable of Verilog?

 

[dave_59]

It would help to clear up some terminology first. Verilog has nets and variables; there is no such thing as a wire variable. See https://go.mentor.com/wire-vs-reg.

When you say drawback, that is a relative term compared to some alternative way of modeling what you want to do. So what is it you want to represent? Also, is there a context associated with you are asking? Simulation or synthesis performance, ect.