race condition verilog
Hi,
Even though reset is an asynchronous signal it has to satisfy removal & recovery timing requirements for proper functioning of the flop. The reset signal can be deasserted only after the removal time, otherwise it will result in metastability.
Removal time is the minimum amount of time that an asyn control signal must be stable after the clock active-edge transition,when asyn signal is deasserted
If reset is deasserted at the active edge of the clock, the output of the flop will become unpredictable, it can either latch the data or remain in reset state