Verilog: question with blocking assignment

[Cluny]

Hi,

I want to calculate the minimum of two values compared to an older minimum value. And I want to do this in one cycle. In my calculation I take the first value and compare it with the old minimum value. Then I take the new (maybe) minimum value and compare it with the second element.

I think that I can only realize this with blocking assignments? for example in the following simplified way:

always @(*)
begin
  if (value[0] < min)
     min = value1;
   if (value[1] < min)
      min = value2;
end

always @(posedge clk)
begin
   min_out <= min;
end

My question: Is there any better way to do this??? Because if I want to synthesize the code, a lot of warnings, due to the produced latch, are reported.

Cluny

 

[ljxpjpjljx]

waning is due to the incomplement of your if block , you can add else block !

 

[dcreddy1980]

Hi,

May be this is what u want, if not try to give some example/better explanation :

i will assume x and y as two inputs of 2-bit wide. The below code can written more efficiently but i just wanted to check with you whether this is what you wanted interms of functionality

input [1:0] x,y;

wire [1;0] min_x_y, min_old_new;
reg [1:0] min_old;

assign min_x_y = (x < y) ? x : y;

assign min_old_new = (min_old < min_x_y) ? min_old : min_x_y;

always@(posedge reset or posedge clock)
begin
if(reset)
min_old <= 0;
else
min_old <= min_old_new;
end


Regards,
dcreddy

 

[Cluny]

Thanks for the hints. The real program I've written is more complex than my simple example has shown. I want to get the minimum of a lot of values and want to take two values and check them at once (in one cycle). The calculated min_out is the new minimum which I have to compare with the next two values and so on...

I think I've founded what my problem was. In the comb always block I used the min value as an "input" and not the feedback value of the output register min_out. With respect to my original example a better version, which does not produce a latch, would be:

always @(*)
begin
  min = min_out  // min is loaded by previous value of min_out, no latch is produced
  if (value[0] < min)
     min = value1;
   if (value[1] < min)
      min = value2;
end

always @(posedge clk)
begin
   min_out <= min;
end

Bye, Cluny

 

[dcreddy1980]

hi cluny,

Its bit strange u r logic, lets assume this scenario :

value[0] = 2
value[1] = 3
min_out = 4

u r min value after the always block will be : min = 3

Is this waht you want??? The requirement looks strange, Ideally i would have expected value[0] and value[1] compared first and then the resultant value is compared against the previous minimum number which is how i have implemented.

Any how if this is what u want, its fine with me.

Regards,
dcreddy

 

[Cluny]

Hi dcreddy1980,

I don't really know why your result would be 3???
There are blocking assignments in the always block, which are successively executed. I suppose that this leads to the right and desired result.

min = min_out          // min = 4
if (value[0] < min)    // right, 2 < 4
  min = value[0];      // min = 2
if (value[1] < min)    // false, 3 < 2
  min = value[1];      // min = 2

Nevertheless, the main problem was the produced latch...
So for me this problem is solved.

cluny

 

[dcreddy1980]

cluny, agreed with u r explanation.