Z80
Full Member level 1
lint verilog unreachable register
Most Verilog preprocessors suck at error reporting if you ask me. For instance, once I mispelled the name of a net, and since the simulator I used considered it an implicit net declaration, it took me a few hours to track down the problem. So the need for linting tools (tools for source code analysis, possible error detection, etc). Do you use any?
PS: if one wants to post a HDL specific question (not programmable logic or asic specific), which is the most appropriate section?
Most Verilog preprocessors suck at error reporting if you ask me. For instance, once I mispelled the name of a net, and since the simulator I used considered it an implicit net declaration, it took me a few hours to track down the problem. So the need for linting tools (tools for source code analysis, possible error detection, etc). Do you use any?
PS: if one wants to post a HDL specific question (not programmable logic or asic specific), which is the most appropriate section?