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Verilog question - do you use linting tools?

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Z80

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lint verilog unreachable register

Most Verilog preprocessors suck at error reporting if you ask me. For instance, once I mispelled the name of a net, and since the simulator I used considered it an implicit net declaration, it took me a few hours to track down the problem. So the need for linting tools (tools for source code analysis, possible error detection, etc). Do you use any?

PS: if one wants to post a HDL specific question (not programmable logic or asic specific), which is the most appropriate section?
 

nand_gates

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Yes I agree with you!
I am using hal from Cadence. But Verix is too good linting tool. It does lot
more than just linting. I use Verix too.

-nand_gates
 

cawan

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Yes, we need linting tools as well especially for verilog design. In most of the case, all the common mistake can be detected especially register size mismatch that could cause severe problem in system operation. I recommend nLint as linting tool.
 

jimjim2k

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Hi

nlinit from novas is a fine linting tool.

tnx
 

phone

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We use spyglass a very good tool for linting.
 

mark_yeh

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nLint from Debussy is a good tool to do this.
 

wadaye

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Except the nL1nt, Led@ from syn0psys is another good choice.
 

jyr_jackchen

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leda will give you many strange info. and make you puzzled.
 

khorram

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0-In and Verisity are the best corporations which have different lint tool. 0-In works on Semi-formal Verification and Verisity works on Formal Verification. They have some lint tools which indicate syntax error, case uncomplete, if condition uncomplete, unreachable states and etc.

Regards,
KH
 

power-twq

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Yes, we always use lint tools to check coding style and

problems on DFT, SYN.




Z80 said:
Most Verilog preprocessors suck at error reporting if you ask me. For instance, once I mispelled the name of a net, and since the simulator I used considered it an implicit net declaration, it took me a few hours to track down the problem. So the need for linting tools (tools for source code analysis, possible error detection, etc). Do you use any?

PS: if one wants to post a HDL specific question (not programmable logic or asic specific), which is the most appropriate section?
 

shiv_emf

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Oops vry old topic ..but again hey is any of linting tool available for students ie free?/
 

aji_vlsi

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haytham

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Hi
Linting is important. Customer may ask to have the lint report :)
We use 0-in, Design Analyst.

Thanks
 

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