Verilog problem Array sizing

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mc_navman

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clog2 clogb2

Hi,

I want to set arraysize based on the max value to be represented. Is this possible in verilog?
i.e.

parameter CLK_DIV = 27210;

reg [14..0]CLK_DIV_REG; //<<-- how do I set this array size automatically for when I change the parameter.
 

verilog max value in array

parameter CLK_DIV = 27210;
reg [CLK_DIV-1 : O] CLK_DIV_REG;

or

parameter CLK_DIV =27210;
reg [31:0] CLK_DIV_REG [CLK_DIV-1 :0];
 

verilog set parameter array to 1

Thanks. But I worked out how to do it in the end. Your example will give 27209 bits to represent a number that is one big number.

Here is the way that works.

parameter CLK_DIVISION_FACTOR = 131;
localparam DIV_BITS = clog2(ADC_CLK_DIVISION_FACTOR);

//define the clogb2 function
//this function returns the celing of the log2 of an input value
// ie log2(200) returns 8 (8 bits to represent)
function integer clog2;
input [31:0] value;
begin
value = value - 1;
for (clog2 = 0; value > 0; clog2 = clog2 + 1)
value = value >> 1;
end
endfunction

the function must be in the module. I am using a `include to include it in the module.
 

changing array sizes dynamically in verilog

that's impossible to realize your intent

by such writing. early ASSEMBLER language

can support such writing.

best regards







mc_navman said:
Hi,

I want to set arraysize based on the max value to be represented. Is this possible in verilog?
i.e.

parameter CLK_DIV = 27210;

reg [14..0]CLK_DIV_REG; //<<-- how do I set this array size automatically for when I change the parameter.
Click to expand...
 

verilog clogb2 10

i don't think it's a good idea. if u need do this .i think you should use built-in RAM in FPGA.
 

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