Verilog n-bit wide 2x1 Mux

[vickyuet]

Dear All,

I had written verilog HDL behavioral code for 4 bit 2x1 mux but my requirement is that i want a generalized code so that i can call it from top level module based upon width of my data.

I want that mux code to behave as 4-bit wide 2X1 mux or on requirement 8-bit wide 2x1 mux as well in same design.Any suggestion how can i adjust this bit width problem in verilog.One way is to call that 4-bit wide 2x1 mux twice to get functionality of 8-bit wide 2x1 mux but i do not want that.Actually my requirement in a design is to use 4 bit 2X1 mux as well as 8-bit 2X1 mux that i intend 2 implement from a general n-bit 2x1 mux.

regards

 

[FvM]

The mux is just one line of behavioral code, using assign out=(sel)?in2:in1, the bitwidth should be defined by module defparam, that can be changed in the instantiation.

 

[vickyuet]

yes i knew code for mux as well as defparam too.but defparam is non-synthesizable construct so it is ruled out too.any other way of doing it..

 

[dcreddy1980]

FYI "defparam" is synthesizable. Will be interesting to know which synthesis tool is not supporting "defparam" construct.

For your scenario, you can implement like this :

mux #(.WIDTH(4)) mux_1(.sel(sel0),.a(a0),.b(b0),z(z0));
mux #(.WIDTH(8)) mux_2(.sel(sel1),.a(a1),.b(b1),z(z1));

module mux(sel,a,b,z);
input [WIDTH-1:0] a,b;
output [WIDTH-1:0]z;
input sel;

assign z = sel ? a : b;
endmodule

 

[vickyuet]

I had read it in books and googled it before writing it in post.Please browse it to topic 14.4 Unsupposrted constructs of this link and tell me as well.
htttp://eesun.free.fr/DOC/VERILOG/verilog_manual1.html
Yes your second parametrized approach is right.Thanks for it.

 

[dcreddy1980]

There is no LRM which states what are synthesizable constructs.

defparam is supported by XST(Xilinx), Synplify Pro, Synopsys-DC if i remember correctly.

To give you an example : "initial" construct is supported by XST(ex : to initialize memory), where as Synplify pro does not support.