Verilog module hierarchy and nets

[ktsangop]

Hello everyone!

I have a question for a module design in verilog.

I have two modules as this :

module top(...IN,....,OUT);
...
reg [7:0] in_register;
reg [7:0] out_register;
 
wire [7:0] wire_in;
wire [7:0] wire_out;

assign wire_in=in_register;
...
bottom instance1(..... wire_in, ....., wire_out);
...
endmodule 

module bottom (......data_in, ......, data_out);
...........
endmodule

So the top module sends data through wire_in to the bottom module and gets data back through wire_out.
I want to store the wire_out data to the out_register before i send it to the OUT.
How can i do this? I cannot use an assignment and i am stuck in here...

Thanks in advance!