[Verilog] Modelsim problem of enum in simulation

sqx · Sep 21, 2018

For system verilog, I use "typedef enum {WAIT, WATCH, ASSERT} STATE;" in both module and testbench. The compiling is passed but when starting simulation, here comes the error:

** Error: (vsim-3906) F:/modelsim_projects/4/test_cd.v(23): Connection type 'test_cd_v_unit.enum int ' is incompatible with 'fsm_cd_v_unit.enum int ' for port (state): Enum types must match.

In both module and testbench, I use "STATE state, n_state; " for the definition of input and output. I think nothing is wrong but how can I make the simulation working?

dave_59 · Sep 21, 2018

You must have only one typedef for STATE. Put it in a common package.

sqx · Sep 23, 2018

Thanks! I defined STATE in a .vh file and included this file in both module an testbench, but Modelsim still created 2 unit packages. How can I fix this problem?

dave_59 · Sep 23, 2018

You need to put your typedef in a common package, then import the package into both modules. See https://go.mentor.com/package-import-versus-include

[Verilog] Modelsim problem of enum in simulation

sqx

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[Verilog] Modelsim problem of enum in simulation

sqx

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