verilog Memory&task

[Mina Magdy]

Hi all
i have many question please help me
1)how could i access a RAM many time in one clock cycle.?
2)can memory (RAM) made inside aTASK not a module?
3)what is the different between Task & module ? i mean if no different why usually it is not prefered to use task on declearation on Hierarchical modules?

please answer me thank you in advance.

 

[TrickyDicky]

1. No
2. No
3. A task is just a way to wrap up a set of assignments into a nice easy to read call. It is just that - a task. A module is like a chip on a circuit board. You couldnt put a task on a circuit board, you need a chip. And that chip might have a task to do.

 

[Mina Magdy]

Re: verilog Memory&task

what would i do if i want to intiallize a memory by some value
my problem is how then to make operation on the Ram like

	reg [3:0] i;
	wire [14:0] address;
	wire [3:0] no_of_bits;
	reg [5:0] A;
	reg CEB,WEB,OEB;
	reg [5:0] INN,OUTT;
	always@(posedge clk)
	begin
	if(start_decoding==1)
	begin
	// first step is to initiallize the H-matrix (the memory)
	 
	 for(address=0;address<16200;address=address+1)
	 begin
	 edgy_ROM_check U2(.address(address),.no_of_bits(no_of_bits));
	 for(i=0;i<10;i=i+1)
	 begin 
	 if(i<no_of_bits)
	 begin
	 A=address+i;
	 INN=llr_stream[i];
	 H_mat_MEM_1 U1(.A(A), .CEB(CEB), .WEB(WEB), .OEB(OEB), .INN(INN), .OUTT(OUTT));
	 end
	 end 
	 end

	end
	end

- - - Updated - - -

Thank you
could you tell me any trick to declare amodule inside a forloop

 

[TrickyDicky]

you could initialise the memory only when you declare the ram, or in an initial block, not inside an always block.

you cannot instantiate modules like that. Remember, a module is like a chip on a circuit board. You cannot add and remove chips while the board is running.

 

[Mina Magdy]

was intial block synthesis

 

[TrickyDicky]

come again?

 

[Mina Magdy]

Re: verilog Memory&task

what i think is in stead of making one large memory i can make alot of small memories(small RAMs) and work on them in the same clock
but the problem faced me is that i need to make some interleaving but it is done to the big RAM
what should i do?

- - - Updated - - -

what i think is in stead of making one large memory i can make alot of small memories(small RAMs) and work on them in the same clock
but the problem faced me is that i need to make some interleaving but it is done to the big RAM
what should i do?

 

[mrflibble]

How about describing FUNCTIONALLY what you want to do? I get the feeling that interleaving memory is not the end goal, but something you thought up to solve whatever your design problem is.

Are you trying to initialize your RAM? If yes, use for example an initial block, or specify a .coe file when you pointey-clickey your ram module in core generator.